PDF 8735-31 Data sheet ( Hoja de datos )

Número de pieza	8735-31
Descripción	Differential-to-3.3V LVPECL Zero Delay Clock Generator
Fabricantes	IDT
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No Preview Available ! 1:5, Differential-to-3.3V LVPECL Zero Delay Clock Generator 8735-31 Data Sheet General Description The 8735-31 is a highly versatile 1:5 Differential -to-3.3V LVPECL Clock Generator. The 8735-31 has a fully integrated PLL and can be configured as zero delay buffer, multiplier or divider, and has an output frequency range of 15.625MHz to 350MHz. The reference divider, feedback divider and output divider are each programmable, thereby allowing for the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. The external feedback allows the device to achieve “zero delay” between the input clock and the output clocks. The PLL_SEL pin can be used to bypass the PLL for system test and debug purposes. In bypass mode, the reference clock is routed around the PLL and into the internal output dividers. Features • Five differential 3.3V LVPECL output pairs • Selectable differential clock inputs • CLKx/nCLKx pairs can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • Output frequency range: 15.625MHz to 350MHz • Input frequency range: 15.625MHz to 350MHz • VCO range: 250MHz to 700MHz • External feedback for “zero delay” clock regeneration with configurable frequencies • Programmable dividers allow for the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8 • Cycle-to-cycle jitter: 60ps (maximum) • Output skew: 35ps (maximum) • Static phase offset: 55ps ± 125ps • Full 3.3V supply voltage • 0°C to 70°C ambient operating temperature • Available in lead-free (RoHS 6) package Block Diagram PLL_SEL Pullup CLK0 Pulldown nCLK0 Pullup CLK1 Pulldown nCLK1 Pullup CLK_SEL Pulldown FB_IN Pulldown nFB_IN Pullup 0 1 ÷2, ÷4, ÷8, ÷16, ÷32,÷64, ÷128 PLL 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8 0 1 SEL0 Pulldown SEL1 Pulldown SEL2 Pulldown SEL3 Pulldown MR Pulldown Q0 nQ0 Q1 nQ1 Q2 nQ2 Q3 nQ3 Q4 nQ4 ©2016 Integrated Device Technology, Inc 1 Pin Assignment SEL0 SEL1 CLK0 nCLK0 CLK1 nCLK1 CLK_SEL MR 32 31 30 29 28 27 26 25 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 10 11 12 13 14 15 16 VCCO Q3 nQ3 Q2 nQ2 Q1 nQ1 VCCO 8735-31 32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View Revision B January 27, 2016 1 page 8735-31 Data Sheet Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Supply Voltage, VCC Inputs, VI Outputs, IO Continuos Current Surge Current Package Thermal Impedance, JA Storage Temperature, TSTG Rating 4.6V -0.5V to VCC + 0.5V 50mA 100mA 47.9C/W (0 lfpm) -65C to 150C DC Electrical Characteristics Table 4A. Power Supply DC Characteristics, VCC = VCCA = VCCO = 3.3V ± 5%, VEE = 0V, TA = 0°C to 70°C Symbol Parameter Test Conditions Minimum Typical Maximum VCC VCCA VCCO IEE ICCA Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current 3.135 3.135 3.135 3.3 3.465 3.3 3.465 3.3 3.465 150 15 Units V V V mA mA Table 4B. LVCMOS/LVTTL DC Characteristics, VCC = VCCA = VCCO = 3.3V ± 5%, VEE = 0V, TA = 0°C to 70°C Symbol Parameter Test Conditions Minimum Typical Maximum VIH Input High Voltage VIL Input Low Voltage CLK_SEL, IIH Input High Current SEL[0:3], MR PLL_SEL CLK_SEL, IIL Input Low Current SEL[0:3], MR PLL_SEL VCC = VIN = 3.465V VCC = VIN = 3.465V VCC = 3.465V, VIN = 0V VCC = 3.465V, VIN = 0V 2 -0.3 -5 -150 VCC + 0.3 0.8 150 5 Units V V µA µA µA µA ©2016 Integrated Device Technology, Inc 5 Revision B January 27, 2016 5 Page 8735-31 Data Sheet Differential Clock Input Interface The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 3A to 3F show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example, in Figure 3A, the input termination applies for IDT HiPerClockS open emitter LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 1.8V Zo = 50Ω Zo = 50Ω LVHSTL IDT LVHSTL Driver 3.3V CLK R1 R2 50Ω 50Ω nCLK Differential Input Figure 3A. HiPerClockS CLK/nCLK Input Driven by an IDT Open Emitter HiPerClockS LVHSTL Driver Figure 3B. HiPerClockS CLK/nCLK Input Driven by a 3.3V LVPECL Driver Figure 3C. HiPerClockS CLK/nCLK Input Driven by a 3.3V LVPECL Driver 3.3V R3 HCSL R4 3.3V CLK nCLK Differential Input Figure 3D. HiPerClockS CLK/nCLK Input Driven by a 3.3V LVDS Driver 2.5V SSTL Zo = 60Ω Zo = 60Ω 2.5V R3 120Ω R4 120Ω 3.3V CLK R1 120Ω R2 120Ω nCLK Differential Input Figure 3E. HiPerClockS CLK/nCLK Input Driven by a 3.3V HCSL Driver Figure 3F. HiPerClockS CLK/nCLK Input Driven by a 2.5V SSTL Driver ©2016 Integrated Device Technology, Inc 11 Revision B January 27, 2016 11 Page

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