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PDF 83905 Data sheet ( Hoja de datos )
| Número de pieza | 83905 | |
| Descripción | 1:6 Crystal-to-LVCMOS/LVTTL Fanout Buffer | |
| Fabricantes | IDT | |
| Logotipo |  |
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Low Skew, 1:6 Crystal-to-LVCMOS/
LVTTL Fanout Buffer
83905
Datasheet
General Description
The 83905 is a low skew, 1-to-6 LVCMOS / LVTTL Fanout Buffer.
The low impedance LVCMOS/LVTTL outputs are designed to
drive 50 series or parallel terminated transmission lines. The
effective fanout can be increased from 6 to 12 by utilizing the
ability of the outputs to drive two series terminated lines.
The 83905 is characterized at full 3.3V, 2.5V, and 1.8V, mixed
3.3V/2.5V, 3.3V/1.8V and 2.5V/1.8V output operating supply
mode. Guaranteed output and part-to-part skew characteristics
along with the 1.8V output capabilities makes the 83905 ideal for
high performance, single ended applications that also require a
limited output voltage.
Pin Assignments
Features
• Six LVCMOS / LVTTL outputs
• Outputs able to drive 12 series terminated lines
• Crystal Oscillator Interface
• Crystal input frequency range: 10MHz to 40MHz
• Output skew: 80ps (maximum)
• RMS phase jitter @ 25MHz, (100Hz – 1MHz): 0.26ps (typical),
VDD = VDDO = 2.5V
Offset
Noise Power
100Hz.................-129.7 dBc/Hz
1kHz ...................-144.4 dBc/Hz
10kHz .................-147.3 dBc/Hz
100kHz ...............-157.3 dBc/Hz
• 5V tolerant enable inputs
• Synchronous output enables
• Operating power supply modes:
Full 3.3V, 2.5V, 1.8V
Mixed 3.3V core/2.5V output operating supply
Mixed 3.3V core/1.8V output operating supply
Mixed 2.5V core/1.8V output operating supply
• 0°C to 70°C ambient operating temperature
• Lead-free (RoHS 6) packaging
83905
20-Lead VFQFN
4mm x 4mm x 0.925mm
package body
K Package
Top View
20 19 18 17 16
GND 1
15 BCLK5
GND 2
14 VDDO
BCLK0 3
VDDO 4
13 BCLK4
12 GND
BCLK1 5
11 GND
6 7 8 9 10
Block Diagram
83905
16-Lead SOIC, 150 Mil
3.9mm x 9.9mm x 1.38mm
package body
M Package
Top View
16-Lead TSSOP
4.4mm x 5.0mm x 0.925mm
package body
G Package
Top View
XTAL_OUT
ENABLE2
GND
BCLK0
VDDO
BCLK1
GND
BCLK2
1
2
3
4
5
6
7
8
16 XTAL_IN
15 ENABLE1
14 BCLK5
13 VDDO
12 BCLK4
11 GND
10 BCLK3
9 VDD
XTAL_IN
XTAL_OUT
ENABLE 1
ENABLE 2
SYNCHRONIZE
SYNCHRONIZE
BCLK0
BCLK1
BCLK2
BCLK3
BCLK4
BCLK5
©2016 Integrated Device Technology, Inc.
1
Revision D September 27, 2016
1 page  
83905 Datasheet
Table 4G. LVCMOS/LVTTL DC Characteristics, TA = 0°C to 70°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
VIH
Input
ENABLE1,
High Voltage ENABLE2
VDD = 3.3V ± 5%
VDD = 2.5V ± 5%
VDD = 1.8V ± 0.2V
2
1.7
0.65 * VDD
VIL
Input
ENABLE1,
Low Voltage ENABLE2
VDD = 3.3V ± 5%
VDD = 2.5V ± 5%
VDD = 1.8V ± 0.2V
-0.3
-0.3
-0.3
VDDO = 3.3V ± 5%; NOTE 1
2.6
VOH Output High Voltage
VDDO = 2.5V ± 5%; IOH = -1mA
VDDO = 2.5V ± 5%; NOTE 1
2.0
1.8
VDDO = 1.8V ± 0.2V; NOTE 1
VDDO - 0.3
VDDO = 3.3V ± 5%; NOTE 1
VDDO = 2.5V ± 5%; IOL = 1mA
VOL Output Low Voltage; NOTE 1
VDDO = 2.5V ± 5%; NOTE 1
VDDO = 1.8V ± 0.2V; NOTE 1
VDD + 0.3
VDD + 0.3
VDD + 0.3
0.8
0.7
0.35 * VDD
0.5
0.4
0.45
0.35
V
V
V
V
V
V
V
V
V
V
V
V
V
V
NOTE 1: Outputs terminated with 50 to VDDO/2. See Parameter Measurement Information, Output Load Test Circuit diagrams.
Table 5. Crystal Characteristics
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
Test Conditions
Minimum
10
Typical
Fundamental
Maximum
40
50
7
1
Units
MHz
pF
mW
©2016 Integrated Device Technology, Inc.
5
Revision D September 27, 2016
5 Page 
Parameter Measurement Information, continued
83905 Datasheet
VDDO
Qx 2
VDDO
Qy 2
t sk(b)
Output Skew
BCLK[0:5]
Output Duty Cycle/Pulse Width/Period
20%
BCLK[0:5]
80%
tR
Output Rise/Fall Time
80%
tF
20%
©2016 Integrated Device Technology, Inc.
11
Revision D September 27, 2016
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet 83905.PDF ] | |
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