PDF MAX11101 Data sheet ( Hoja de datos )

Número de pieza	MAX11101
Descripción	200ksps ADC
Fabricantes	Maxim Integrated
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No Preview Available ! 19-6047; Rev 1; 1/12 MAX11101 14-Bit, +5V, 200ksps ADC with 10µA Shutdown General Description The MAX11101 low-power, 14-bit analog-to-digital con- verter (ADC) features a successive approximation ADC, automatic power-down, fast 1.1Fs wake-up, and a high- speed SPI/QSPI™/MICROWIRE®-compatible interface. The MAX11101 operates with a single +5V analog supply and features a separate digital supply, allowing direct interfacing with 2.7V to 5.25V digital logic. At the maximum sampling rate of 200ksps, the MAX11101 typically consumes 2.45mA. Power consumption is typi- cally 12.25mW (VAVDD = VDVDD = 5V) at a 200ksps (max) sampling rate. AutoShutdown™ reduces supply current to 140FA at 10ksps and to less than 10FA at reduced sampling rates. Excellent dynamic performance and low power, com- bined with ease of use and small package size (10-pin FMAXM and 12-bump WLP), make the MAX11101 ideal for battery-powered and data-acquisition applications or for other circuits with demanding power consumption and space requirements. Applications Motor Control Industrial Process Control Industrial I/O Modules Data-Acquisition Systems Thermocouple Measurements Accelerometer Measurements Portable- and Battery-Powered Equipment Ordering Information appears at end of data sheet. Features S 14-Bit Resolution, 1 LSB DNL S +5V Single-Supply Operation S Adjustable Logic Level (2.7V to 5.25V) S Input Voltage Range: 0 to VREF S Internal Track-and-Hold, 4MHz Input Bandwidth S SPI/QSPI/MICROWIRE-Compatible Serial Interface S Small 10-Pin µMAX and WLP Packages S Low Power 2.45mA at 200ksps 140µA at 10ksps 0.1µA in Power-Down Mode Functional Diagram AVDD DVDD REF AIN AGND SCLK CS TRACK-AND- HOLD 14-BIT SAR ADC CONTROL OUTPUT BUFFER DGND MAX11101 DOUT QSPI is a trademark of Motorola, Inc. MICROWIRE is a registered trademark of National Semiconductor Corp. AutoShutdown is a trademark and µMAX is a registered trademark of Maxim Integrated Products, Inc. For related parts and recommended products to use with this part, refer to: www.maxim-ic.com/MAX11101.related �� Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 page MAX11101 14-Bit, +5V, 200ksps ADC with 10µA Shutdown Typical Operating Characteristics (VAVDD = VDVDD = 5V, fSCLK = 4.8MHz, CLOAD = 50pF, VREF = +4.096V, TA = +25°C, unless otherwise noted.) INTEGRAL NONLINEARITY (INL) vs. CODE 0.5 0.4 0.3 0.2 DIFFERENTIAL NONLINEARITY (DNL) vs. CODE 0.5 0.4 0.3 0.2 INL AND DNL vs. ANALOG SUPPLY VOLTAGE 0.5 MAX INL 0.3 0.1 0.1 0.1 00 -0.1 -0.1 MIN DNL -0.1 MAX DNL -0.2 -0.2 -0.3 -0.4 -0.5 0 4096 8192 12288 16384 2048 6144 10240 14336 OUTPUT CODE (DECIMAL) -0.3 -0.4 -1.5 0 4096 8192 12288 16384 2048 6144 10240 14336 OUTPUT CODE (DECIMAL) -0.3 MIN INL -0.5 4.75 4.85 4.95 5.05 5.15 5.25 VAVDD (V) INL AND DNL vs. TEMPERATURE 0.5 MAX INL 0.3 0.1 MAX DNL MIN DNL -0.1 -0.3 -0.5 -40 MIN INL -15 10 35 60 TEMPERATURE (°C) 85 MAX11101 FFT 0 -20 -40 -60 -80 -100 -120 -140 0 10 20 30 40 50 60 70 80 90 100 FREQUENCY (kHz) SINAD VS. FREQUENCY 100 90 80 70 60 50 40 30 20 10 fSAMPLE = 200kHz 0 0.1 1 10 FREQUENCY (kHz) 100 SFDR VS. FREQUENCY 110 100 90 80 70 60 50 40 30 20 10 fSAMPLE = 200kHz 0 0.1 1 10 FREQUENCY (kHz) 100 THD VS. FREQUENCY 0 -10 fSAMPLE = 200kHz -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 0.1 1 10 FREQUENCY (kHz) 100 �� Maxim Integrated Products 5 5 Page MAX11101 14-Bit, +5V, 200ksps ADC with 10µA Shutdown CS SCLK DOUT tDN 1 tCSS 4 6 8 12 16 20 24 tCL tCH tCSH D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 S1 S0 tACQ tDO tTR Figure 6. External Timing Diagram COMPLETE CONVERSION SEQUENCE CS DOUT CONVERSION 0 POWERED UP POWERED DOWN CONVERSION 1 POWERED UP Figure 7. Shutdown Sequence A CS falling edge initiates an acquisition sequence. The analog input is stored in the capacitive DAC, DOUT changes from high impedance to logic-low, and the ADC begins to convert after the sixth clock cycle. SCLK drives the conversion process and shifts out the conversion result on DOUT. SCLK begins shifting out the data (MSB first) after the fall- ing edge of the 8th SCLK pulse. Twenty-four falling clock edges are needed to shift out the eight leading zeros, 14 data bits, and 2 sub-bits (S1 and S0). Extra clock pulses occurring after the conversion result has been clocked out, and prior to the rising edge of CS, produce trail- ing zeros at DOUT and have no effect on the converter operation. Force CS high after reading the conversion’s LSB to reset the internal registers and place the MAX11101 in shutdown. For maximum throughput, force CS low again to initiate the next conversion immediately after the speci- fied minimum time (tCSW). Note: Forcing CS high in the middle of a conversion immediately aborts the conversion and places the MAX11101 in shutdown. �� Maxim Integrated Products 11 11 Page

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