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PDF EPF10K50 Data sheet ( Hoja de datos )

Número de pieza EPF10K50
Descripción Embedded Programmable Logic Device Family
Fabricantes Altera Corporation 
Logotipo Altera Corporation Logotipo



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No Preview Available ! EPF10K50 Hoja de datos, Descripción, Manual

January 2003, ver. 4.2
Includes
FLEX 10KA
FLEX 10K
® Embedded Programmable
Logic Device Family
Data Sheet
Features...
The industry’s first embedded programmable logic device (PLD)
family, providing System-on-a-Programmable-Chip (SOPC)
integration
– Embedded array for implementing megafunctions, such as
efficient memory and specialized logic functions
– Logic array for general logic functions
High density
– 10,000 to 250,000 typical gates (see Tables 1 and 2)
– Up to 40,960 RAM bits; 2,048 bits per embedded array block
(EAB), all of which can be used without reducing logic capacity
System-level features
– MultiVoltTM I/O interface support
– 5.0-V tolerant input pins in FLEX® 10KA devices
– Low power consumption (typical specification less than 0.5 mA
in standby mode for most devices)
– FLEX 10K and FLEX 10KA devices support peripheral
component interconnect Special Interest Group (PCI SIG) PCI
Local Bus Specification, Revision 2.2
– FLEX 10KA devices include pull-up clamping diode, selectable
on a pin-by-pin basis for 3.3-V PCI compliance
– Select FLEX 10KA devices support 5.0-V PCI buses with eight or
fewer loads
– Built-in Joint Test Action Group (JTAG) boundary-scan test
(BST) circuitry compliant with IEEE Std. 1149.1-1990, available
without consuming any device logic
Table 1. FLEX 10K Device Features
Feature
Typical gates (logic and RAM) (1)
Maximum system gates
Logic elements (LEs)
Logic array blocks (LABs)
Embedded array blocks (EABs)
Total RAM bits
Maximum user I/O pins
EPF10K10
EPF10K10A
10,000
31,000
576
72
3
6,144
150
EPF10K20
20,000
63,000
1,152
144
6
12,288
189
EPF10K30
EPF10K30A
30,000
69,000
1,728
216
6
12,288
246
EPF10K40
40,000
93,000
2,304
288
8
16,384
189
EPF10K50
EPF10K50V
50,000
116,000
2,880
360
10
20,480
310
Altera Corporation
DS-F10K-4.2
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EPF10K50 pdf
FLEX 10K Embedded Programmable Logic Device Family Data Sheet
Notes to tables:
(1) FLEX 10K and FLEX 10KA device package types include plastic J-lead chip carrier (PLCC), thin quad flat pack
(TQFP), plastic quad flat pack (PQFP), power quad flat pack (RQFP), ball-grid array (BGA), pin-grid array (PGA),
and FineLine BGATM packages.
(2) This option is supported with a 256-pin FineLine BGA package. By using SameFrame pin migration, all FineLine
BGA packages are pin compatible. For example, a board can be designed to support both 256-pin and 484-pin
FineLine BGA packages. The Altera software automatically avoids conflicting pins when future migration is set.
General
Description
Altera’s FLEX 10K devices are the industry’s first embedded PLDs. Based
on reconfigurable CMOS SRAM elements, the Flexible Logic Element
MatriX (FLEX) architecture incorporates all features necessary to
implement common gate array megafunctions. With up to 250,000 gates,
the FLEX 10K family provides the density, speed, and features to integrate
entire systems, including multiple 32-bit buses, into a single device.
FLEX 10K devices are reconfigurable, which allows 100% testing prior to
shipment. As a result, the designer is not required to generate test vectors
for fault coverage purposes. Additionally, the designer does not need to
manage inventories of different ASIC designs; FLEX 10K devices can be
configured on the board for the specific functionality required.
Table 6 shows FLEX 10K performance for some common designs. All
performance values were obtained with Synopsys DesignWare or LPM
functions. No special design technique was required to implement the
applications; the designer simply inferred or instantiated a function in a
Verilog HDL, VHDL, Altera Hardware Description Language (AHDL), or
schematic design file.
Table 6. FLEX 10K & FLEX 10KA Performance
Application
Resources
Used
LEs EABs
16-bit loadable
counter (1)
16-bit accumulator (1)
16-to-1 multiplexer (2)
256 × 8 RAM read
cycle speed (3)
256 × 8 RAM write
cycle speed (3)
16
16
10
0
0
0
0
0
1
1
-1 Speed
Grade
204
204
4.2
172
106
Performance
-2 Speed
Grade
166
166
5.8
145
89
-3 Speed
Grade
125
125
6.0
108
68
-4 Speed
Grade
95
95
7.0
84
63
Notes:
(1) The speed grade of this application is limited because of clock high and low specifications.
(2) This application uses combinatorial inputs and outputs.
(3) This application uses registered inputs and outputs.
Units
MHz
MHz
ns
MHz
MHz
Altera Corporation
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EPF10K50 arduino
FLEX 10K Embedded Programmable Logic Device Family Data Sheet
Larger blocks of RAM are created by combining multiple EABs. For
example, two 256 × 8 RAM blocks can be combined to form a
256 × 16 RAM block; two 512 × 4 blocks of RAM can be combined to form
a 512 × 8 RAM block. See Figure 3.
Figure 3. Examples of Combining EABs
256 × 16
256 × 8
512 × 8
512 × 4
256 × 8
512 × 4
If necessary, all EABs in a device can be cascaded to form a single RAM
block. EABs can be cascaded to form RAM blocks of up to 2,048 words
without impacting timing. Altera’s software automatically combines
EABs to meet a designer’s RAM specifications.
EABs provide flexible options for driving and controlling clock signals.
Different clocks can be used for the EAB inputs and outputs. Registers can
be independently inserted on the data input, EAB output, or the address
and WE inputs. The global signals and the EAB local interconnect can drive
the WE signal. The global signals, dedicated clock pins, and EAB local
interconnect can drive the EAB clock signals. Because the LEs drive the
EAB local interconnect, the LEs can control the WE signal or the EAB clock
signals.
Each EAB is fed by a row interconnect and can drive out to row and
column interconnects. Each EAB output can drive up to two row channels
and up to two column channels; the unused row channel can be driven by
other LEs. This feature increases the routing resources available for EAB
outputs. See Figure 4.
Altera Corporation
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