PDF 9ZXL0831 Data sheet ( Hoja de datos )

Número de pieza	9ZXL0831
Descripción	Low-power 8-output differential buffer
Fabricantes	IDT
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No Preview Available ! 8-OUTPUT DB800ZL DATASHEET 9ZXL0831 General Description The 9ZXL0831 is a low-power 8-output differential buffer that meets all the performance requirements of the Intel DB800ZL specification. It is suitable for PCI-Express Gen1/2/3 or QPI/UPI applications, and uses a fixed external feedback to maintain low drift for demanding QPI/UPI applications. Recommended Application Buffer for Romley, Grantley and Purley Servers, SSD drives and PCIe Output Features • 8 - LP-HCSL Output Pairs Block Diagram Features/Benefits • Low-power push-pull outputs; Save power and board space - no Rp • Space-saving 48-pin VFQFPN package • Fixed feedback path for 0ps input-to-output delay • 8 OE# pins; hardware control of each output • PLL or bypass mode; PLL can dejitter incoming clock • 100MHz or 133MHz PLL mode operation; supports PCIe and QPI applications • Selectable PLL bandwidth; minimizes jitter peaking in downstream PLL's • Spread Spectrum Compatible; tracks spreading input clock for low EMI Key Specifications • Cycle-to-cycle jitter <50ps • Output-to-output skew <65 ps • Input-to-output delay variation <50ps • PCIe Gen3 phase jitter <1.0ps RMS • QPI/UPI 9.6GT/s 12UI phase jitter <0.2ps RMS OE(7:0)# DIF_IN DIF_IN# HIBW_BYPM_LOBW# 100M_133M# CKPWRGD/PD# Logic SMBDAT SMBCLK Z-PLL (SS Compatible) DFB_OUT_NC DIF(7:0) IDT® 8-OUTPUT DB800ZL 1 9ZXL0831 REV E 081616 1 page 9ZXL0831 8-OUTPUT DB800ZL Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the 9ZXL0831. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. PARAMETER SYMBOL CONDITIONS 3.3V Supply Voltage VDD, VDDA, VDDR VDD for core logic and PLL Input Low Voltage VIL Input High Voltage VIH Except for SMBus interface Input High Voltage VIHSMB SMBus clock and data pins Storage Temperature Ts Junction Temperature Tj Input ESD protection ESD prot Human Body Model 1Guaranteed by design and characterization, not 100% tested in production. 2 Operation under these conditions is neither implied nor guaranteed. MIN GND-0.5 -65 2000 TYP UNITS NOTES MAX 4.6 V 1,2 VDD+0.5V 5.5V 150 125 V V V °C °C V 1 1 1 1 1 1 Electrical Characteristics–DIF_IN Clock Input Parameters (HCSL-compatible) TA = TCOM; Supply Voltage VDD = 3.3 V +/-5% PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES Input Crossover Voltage - DIF_IN Input Swing - DIF_IN Input Slew Rate - DIF_IN VCROSS VSWING dv/dt Cross Over Voltage Differential value Measured differentially Input Leakage Current Input Duty Cycle IIN dtin VIN = VDD , VIN = GND Measurement from differential wavefrom Input Jitter - Cycle to Cycle JDIFIn Differential Measurement 1 Guaranteed by design and characterization, not 100% tested in production. 2Slew rate measured through +/-75mV window centered around differential zero 150 300 0.4 -5 45 0 900 mV 1 mV 1 8 V/ns 1,2 5 uA 55 % 1 125 ps 1 IDT® 8-OUTPUT DB800ZL 5 9ZXL0831 REV E 081616 5 Page 9ZXL0831 8-OUTPUT DB800ZL General SMBus Serial Interface Information for 9ZXL0831 How to Write • Controller (host) sends a start bit • Controller (host) sends the write address • IDT clock will acknowledge • Controller (host) sends the beginning byte location = N • IDT clock will acknowledge • Controller (host) sends the byte count = X • IDT clock will acknowledge • Controller (host) starts sending Byte N through Byte N+X-1 • IDT clock will acknowledge each byte one at a time • Controller (host) sends a Stop bit Index Block Write Operation Controller (Host) T starT bit IDT (Slave/Receiver) Slave Address WR WRite ACK Beginning Byte = N ACK Data Byte Count = X ACK Beginning Byte N ACK O OO OO O Byte N + X - 1 ACK P stoP bit How to Read • Controller (host) will send a start bit • Controller (host) sends the write address • IDT clock will acknowledge • Controller (host) sends the beginning byte location = N • IDT clock will acknowledge • Controller (host) will send a separate start bit • Controller (host) sends the read address • IDT clock will acknowledge • IDT clock will send the data byte count = X • IDT clock sends Byte N+X-1 • IDT clock sends Byte 0 through Byte X (if X(H) was written to Byte 8) • Controller (host) will need to acknowledge each byte • Controller (host) will send a not acknowledge bit • Controller (host) will send a stop bit Index Block Read Operation Controller (Host) T starT bit IDT (Slave/Receiver) Slave Address WR WRite ACK Beginning Byte = N ACK RT Repeat starT Slave Address RD ReaD ACK ACK ACK O O O N Not acknowledge P stoP bit Data Byte Count=X Beginning Byte N O O O Byte N + X - 1 IDT® 8-OUTPUT DB800ZL 11 9ZXL0831 REV E 081616 11 Page

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