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PDF 9ZX21901B Data sheet ( Hoja de datos )
| Número de pieza | 9ZX21901B | |
| Descripción | 19-Output Differential Zbuffer | |
| Fabricantes | IDT | |
| Logotipo |  |
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DATASHEET
19-Output Differential Zbuffer for PCIe Gen2/3 and QPI
9ZX21901B
Description
Features/Benefits
The 9ZX21901 is a version of the Intel DB1900Z Differential Buffer
with an ajdustable external feedback path allowing the user to
eliminate trace delays from their design. It is suitable for PCIe Gen3
or QPI applications. The part is backwards compatible to PCIe
Gen1 and Gen2. The device maintains low drift for critical QPI
applications. In bypass mode, the IDT9ZX21901 can provide outputs
up to 400MHz.
Recommended Application
19 output PCIe Gen3/QPI buffer with adjustable feedback for Romley
platforms
Output Features
• 19 - 0.7V current mode differential HCSL output pairs
•
•
•
•
•
•
•
•
•
External feedback path; Adjustable input-to-output delay
9 Selectable SMBus addresses/ Multiple devices can
share same SMBus segment
8 dedicated OE# pins/ hardware control of outputs
PLL or bypass mode/ PLL can dejitter incoming clock
Selectable PLL BW/ minimizes jitter peaking in
downstream PLL's
Spread spectrum compatible/tracks spreading input clock
for EMI reduction
SMBus Interface/ unused outputs can be disabled
100MHz & 133.33MHz PLL mode/ Legacy QPI support
Undriven differential outputs in Power Down mode for
maximum power savings
Key Specifications
• Cycle-to-cycle jitter: < 50ps
• Output-to-output skew: <65ps
• Input-to-output delay: User adjustable
• Input-to-output delay variation: <50ps
• Phase jitter: PCIe Gen3 < 1ps rms
Functional Block Diagram
• Phase jitter: QPI 9.6GB/s < 0.2ps rms
OE(5_12)#
8
DIF_IN
DIF_IN#
DFB_IN
DFB_IN#
HIBW_BYPM_LOBW#
100M_133M#
CKPWRGD/PD#
SMB_A0_tri
SMB_A1_tri
SMBDAT
SMBCLK
Logic
Z-PLL
(SS Compatible)
DFB_OUT
DIF(18:0)
IREF
IDT® 19-Output Differential Zbuffer for PCIe Gen2/3 and QPI
1
1586P - 11/19/15
1 page  
9ZX21901B
19-Output Differential Zbuffer for PCIe Gen2/3 and QPI
Electrical Characteristics - Absolute Maximum Ratings
PARAMETER
SYMBOL
CONDITIONS
3.3V Core Supply Voltage VDDA
3.3V Logic Supply Voltage VDD
Input Low Voltage
VIL
Input High Voltage
VIH
Except for SMBus interface
Input High Voltage
VIHSMB
SMBus clock and data pins
Storage Temperature
Ts
Junction Temperature
Tj
Case Temperature
Tc
Input ESD protection ESD prot
Human Body Model
1Guaranteed by design and characterization, not 100% tested in production.
2 Operation under these conditions is neither implied nor guaranteed.
MIN
GND-0.5
-65
2000
TYP
UNITS NOTES
MAX
4.6 V 1,2
4.6 V 1,2
V1
VDD+0.5V
5.5V
V
V
1
1
150 °C 1
125 °C 1
110 °C 1
V1
Electrical Characteristics - Input/Supply/Common Parameters
TA = TCOM; Supply Voltage VDD/VDDA = 3.3 V +/-5%, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
Ambient Operating
Temperature
Input High Voltage
Input Low Voltage
TCOM
VIH
VIL
Commmercial range
Single-ended inputs, except SMBus, low
threshold and tri-level inputs
Single-ended inputs, except SMBus, low
threshold and tri-level inputs
0
2
GND - 0.3
IIN Single-ended inputs, VIN = GND, VIN = VDD -5
Input Current
Single-ended inputs
IINP
VIN = 0 V; Inputs with internal pull-up resistors
-200
VIN = VDD; Inputs with internal pull-down resistors
TYP
MAX
70
UNITS NOTES
°C 1
VDD + 0.3 V
0.8 V
5 uA
1
1
1
200 uA 1
Input Frequency
Pin Inductance
Capacitance
Fibyp
Fipll
Fipll
Lpin
CIN
CINDIF_IN
VDD = 3.3 V, Bypass mode
VDD = 3.3 V, 100MHz PLL mode
VDD = 3.3 V, 133.33MHz PLL mode
Logic Inputs, except DIF_IN
DIF_IN differential clock inputs
33 400
90 100.00 105
120 133.33 140
7
1.5 5
1.5 2.7
MHz
MHz
MHz
nH
pF
pF
2
2
2
1
1
1,4
COUT
Output pin capacitance
6 pF 1
Clk Stabilization
TSTAB
From VDD Power-Up and after input clock
stabilization or de-assertion of PD# to 1st clock
1.8 ms 1,2
Input SS Modulation
Frequency
OE# Latency
fMODIN
tLATOE#
Allowable Frequency
(Triangular Modulation)
DIF start after OE# assertion
DIF stop after OE# deassertion
30
4
33 kHz 1
12 clocks 1,3
Tdrive_PD#
tDRVPD
DIF output enable after
PD# de-assertion
300 us 1,3
Tfall
Trise
SMBus Input Low Voltage
SMBus Input High Voltage
SMBus Output Low Voltage
SMBus Sink Current
Nominal Bus Voltage
SCLK/SDATA Rise Time
SCLK/SDATA Fall Time
SMBus Operating
Frequency
tF
tR
VILSMB
VIHSMB
VOLSMB
IPULLUP
VDDSMB
tRSMB
tFSMB
fMAXSMB
Fall time of control inputs
Rise time of control inputs
@ IPULLUP
@ VOL
3V to 5V +/- 10%
(Max VIL - 0.15) to (Min VIH + 0.15)
(Min VIH + 0.15) to (Max VIL - 0.15)
Maximum SMBus operating frequency
2.1
4
2.7
5
5
0.8
VDDSMB
0.4
5.5
1000
300
100
ns
ns
V
V
V
mA
V
ns
ns
kHz
1,2
1,2
1
1
1
1
1
1
1
1,5
1Guaranteed by design and characterization, not 100% tested in production.
2Control input must be monotonic from 20% to 80% of input swing.
3Time from deassertion until outputs are >200 mV
4 DIF_IN input
5The differential input clock must be running for the SMBus to be active
IDT® 19-Output Differential Zbuffer for PCIe Gen2/3 and QPI
1586P - 11/19/15
5
5 Page 
9ZX21901B
19-Output Differential Zbuffer for PCIe Gen2/3 and QPI
SMBusTable: PLL Mode, and Frequency Select Register
Byte 0 Pin #
Name
Control Function
Bit 7
5
PLL Mode 1
PLL Operating Mode Rd back 1
Bit 6
5
PLL Mode 0
PLL Operating Mode Rd back 0
Bit 5
72/71
DIF_18_En
Output Control overrides OE# pin
Bit 4
70/69
DIF_17_En
Output Control overrides OE# pin
Bit 3
67/66
DIF_16_En
Output Control overrides OE# pin
Bit 2
Reserved
Bit 1
Reserved
Bit 0
4
100M_133M#
Frequency Select Readback
SMBusTable: Output Control Register
Byte 1 Pin #
Name
Bit 7
39/38
DIF_7_En
Bit 6
35/36
DIF_6_En
Bit 5
32/33
DIF_5_En
Bit 4
29/30
DIF_4_En
Bit 3
27/28
DIF_3_En
Bit 2
24/25
DIF_2_En
Bit 1
22/23
DIF_1_En
Bit 0
19/20
DIF_0_En
Control Function
Output Control overrides OE# pin
Output Control overrides OE# pin
Output Control overrides OE# pin
Output Control overrides OE# pin
Output Control overrides OE# pin
Output Control overrides OE# pin
Output Control overrides OE# pin
Output Control overrides OE# pin
SMBusTable: Output Control Register
Byte 2 Pin #
Name
Bit 7
65/64
DIF_15_En
Bit 6
62/61
DIF_14_En
Bit 5
60/59
DIF_13_En
Bit 4
56/55
DIF_12_En
Bit 3
53/52
DIF_11_En
Bit 2
50/49
DIF_10_En
Bit 1
47/46
DIF_9_En
Bit 0
42/41
DIF_8_En
Control Function
Output Control overrides OE# pin
Output Control overrides OE# pin
Output Control overrides OE# pin
Output Control overrides OE# pin
Output Control overrides OE# pin
Output Control overrides OE# pin
Output Control overrides OE# pin
Output Control overrides OE# pin
SMBusTable: Output Enable Pin Status Readback Register
Byte 3 Pin #
Name
Control Function
Bit 7
57
OE_RB12
Real Time readback of OE#12
Bit 6
54
OE_RB11
Real Time readback of OE#11
Bit 5
51
OE_RB10
Real Time readback of OE#10
Bit 4
48
OE_RB9
Real Time readback of OE#9
Bit 3
43
OE_RB8
Real Time readback of OE#8
Bit 2
40
OE_RB7
Real Time readback of OE#7
Bit 1
37
OE_RB6
Real Time readback of OE#6
Bit 0
34
OE_RB5
Real Time readback of OE#5
Type
R
R
RW
RW
RW
R
01
See PLL Operating Mode
Readback Table
Hi-Z Enable
Hi-Z Enable
Hi-Z Enable
133MHz
100MHz
Default
Latch
Latch
1
1
1
0
0
Latch
Type
0
1 Default
RW 1
RW 1
RW 1
RW
Hi-Z
Enable
1
RW 1
RW 1
RW 1
RW 1
Type
0
1 Default
RW 1
RW 1
RW 1
RW
Hi-Z
Enable
1
RW 1
RW 1
RW 1
RW 1
Type
R
R
R
R
R
R
R
R
0
OE# pin Low
1
OE# Pin High
Default
Real time
Real time
Real time
Real time
Real time
Real time
Real time
Real time
IDT® 19-Output Differential Zbuffer for PCIe Gen2/3 and QPI
11
1586P - 11/19/15
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet 9ZX21901B.PDF ] | |
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