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PDF 9ZXL0651 Data sheet ( Hoja de datos )

Número de pieza 9ZXL0651
Descripción 6-OUTPUT LOW-POWER HCSL BUFFER
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6-OUTPUT LOW-POWER HCSL BUFFER FOR PCIE GEN1-2-3 AND QPI
DATASHEET
9ZXL0651
General Description
The 9ZXL0651 is a low-power 6-output differential buffer
that meets all the performance requirements of the Intel
DB1200Z specification. It consumes 50% less power than
standard HCSL devices and has internal terminations to
allow direct connection to 85 ohm transmission lines. The
9ZXL0651 is backwards compatible to PCIe Gen1 and
Gen2 and QPI 6.4GT/s specifications. A fixed, internal
feedback path maintains low drift for critical QPI
applications.
Recommended Application
6-Output Low-Power HCSL Buffer for PCIe Gen1-2-3 and
QPI
Output Features
6 - 0.7V low-power HCSL (LP-HCSL) output pairs
w/integrated terminations
Block Diagram
Features/Benefits
Low-Power-HCSL outputs w/Zo = 85; save power and
board space - no termination resistors required. Ideal for
blade servers.
Space-saving 40-pin VFQFPN package
Fixed feedback path for 0ps input-to-output delay
6 OE# pins; Hardware control of each output
PLL or bypass mode; PLL can dejitter incoming clock
Selectable PLL bandwidth; minimizes jitter peaking in
downstream PLL's
Spread Spectrum Compatible; tracks spreading input
clock for low EMI
Key Specifications
Cycle-to-cycle jitter <50ps
Output-to-output skew <65 ps
Input-to-output delay variation <50ps
PCIe Gen3 phase jitter <1.0ps RMS
QPI 9.6GT/s 12UI phase jitter <0.2ps RMS
OE(5:0)#
DIF_IN
DIF_IN#
HIBW_BYPM_LOBW#
CKPWRGD/PD#
SMBDAT
SMBCLK
Logic
Z-PLL
(SS Compatible)
DFB_OUT_NC
DIF(5:0)
IDT® 6-OUTPUT LOW-POWER HCSL BUFFER FOR PCIE GEN1-2-3 AND QPI
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9ZXL0651
REV C 040115

1 page




9ZXL0651 pdf
9ZXL0651
6-OUTPUT LOW-POWER HCSL BUFFER FOR PCIE GEN1-2-3 AND QPI
Electrical Characteristics–Input/Supply/Common Parameters
TA = TCOM; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS NOTES
Ambient Operating
Temperature
Input High Voltage
Input Low Voltage
Input Current
TCOM
VIH
VIL
IIN
IINP
Commmercial range
0 35 70 °C
Single-ended inputs, except SMBus, low
threshold and tri-level inputs
Single-ended inputs, except SMBus, low
threshold and tri-level inputs
Single-ended inputs, VIN = GND, VIN = VDD
2
GND - 0.3
-5
Single-ended inputs
VIN = 0 V; Inputs with internal pull-up resistors
VIN = VDD; Inputs with internal pull-down resistors
-200
VDD + 0.3 V
0.8 V
5 uA
200 uA
1
1
1
1
1
Input Frequency
Fibyp
Fipll
VDD = 3.3 V, Bypass mode
VDD = 3.3 V, 100MHz PLL mode
1 150 MHz 2
90 100.00 110 MHz 2
Pin Inductance
Lpin
7 nH 1
Capacitance
CIN
CINDIF_IN
Logic Inputs, except DIF_IN
DIF_IN differential clock inputs
1.5
1.5
5 pF 1
2.7 pF 1,4
COUT
Output pin capacitance
6 pF 1
Clk Stabilization
TSTAB
From VDD Power-Up and after input clock
stabilization or de-assertion of PD# to 1st clock
0.53 1 ms 1,2
Input SS Modulation
Frequency
fMODIN
Allowable Frequency
(Triangular Modulation)
30
33 kHz 1
OE# Latency
tLATOE#
DIF start after OE# assertion
DIF stop after OE# deassertion
4 8 12 cycles 1,3
Tdrive_PD#
tDRVPD
DIF output enable after
PD# de-assertion
300 us 1,3
Tfall tF Fall time of control inputs
10 ns 1,2
Trise tR Rise time of control inputs
10 ns 1,2
SMBus Input Low Voltage
VILSMB
0.8 V 1
SMBus Input High Voltage VIHSMB
2.1
VDDSMB
V
1
SMBus Output Low Voltage VOLSMB
@ IPULLUP
0.4 V 1
SMBus Sink Current
IPULLUP
@ VOL
4
mA 1
Nominal Bus Voltage
VDDSMB
3V to 5V +/- 10%
2.7 5.5 V 1
SCLK/SDATA Rise Time
tRSMB
(Max VIL - 0.15) to (Min VIH + 0.15)
1000
ns
1
SCLK/SDATA Fall Time
SMBus Operating
Frequency
tFSMB
fMAXSMB
(Min VIH + 0.15) to (Max VIL - 0.15)
Maximum SMBus operating frequency
300 ns 1
100 kHz 1,5
1Guaranteed by design and characterization, not 100% tested in production.
2Control input must be monotonic from 20% to 80% of input swing.
3Time from deassertion until outputs are >200 mV
4DIF IN input
5The differential input clock must be running for the SMBus to be active
IDT® 6-OUTPUT LOW-POWER HCSL BUFFER FOR PCIE GEN1-2-3 AND QPI
5
9ZXL0651
REV C 040115

5 Page





9ZXL0651 arduino
9ZXL0651
6-OUTPUT LOW-POWER HCSL BUFFER FOR PCIE GEN1-2-3 AND QPI
SMBusTable: PLL Mode, and Frequency Select Register
Byte 0 Pin #
Name
Control Function
Type
0
1 Default
Bit 7
2
PLL Mode 1
PLL Operating Mode Rd back 1
R
See PLL Operating Mode
Latch
Bit 6
2
PLL Mode 0
PLL Operating Mode Rd back 0
R
Readback Table
Latch
Bit 5
Reserved
0
Bit 4
Reserved
0
Bit 3
PLL_SW_EN
Enable S/W control of PLL BW
RW HW Latch SMBus Control 0
Bit 2
PLL Mode 1
PLL Operating Mode 1
RW
See PLL Operating Mode
1
Bit 1
PLL Mode 0
PLL Operating Mode 1
RW
Readback Table
1
Bit 0
Reserved
1
Note: Setting bit 3 to '1' allows the user to overide the Latch value from pin 5 via use of bits 2 and 1. Use the values from the PLL Operating
Mode Readback Table. Note that Bits 7 and 6 will keep the value originally latched on pin 5. A warm reset of the system will have to
accomplished if the user changes these bits.
SMBusTable: Output Control Register
Byte 1 Pin #
Name
Bit 7
Bit 6
26/27
DIF_3_En
Bit 5
23/24
DIF_2_En
Bit 4
Bit 3
Bit 2
17/18
DIF_1_En
Bit 1
14/15
DIF_0_En
Bit 0
SMBusTable: Output Control Register
Byte 2 Pin #
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
36/37
DIF_5_En
Bit 1
33/34
DIF_4_En
Bit 0
SMBusTable: Reserved Register
Byte 3 Pin #
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SMBusTable: Reserved Register
Byte 4 Pin #
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Control Function
Reserved
Output Control - '0' overrides OE# pin
Output Control - '0' overrides OE# pin
Reserved
Reserved
Output Control - '0' overrides OE# pin
Output Control - '0' overrides OE# pin
Reserved
Type
RW
RW
RW
RW
Control Function
Reserved
Reserved
Reserved
Reserved
Reserved
Output Control - '0' overrides OE# pin
Output Control - '0' overrides OE# pin
Reserved
Type
RW
RW
Control Function
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Type
Control Function
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Type
0
Low/Low
Low/Low
0
Low/Low
0
0
1
Enable
Enable
Default
1
1
1
1
1
1
1
1
1
Enable
Default
0
0
0
0
1
1
1
1
1 Default
0
0
0
0
0
0
0
0
1 Default
0
0
0
0
0
0
0
0
IDT® 6-OUTPUT LOW-POWER HCSL BUFFER FOR PCIE GEN1-2-3 AND QPI
11
9ZXL0651
REV C 040115

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