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PDF 9ZX21200 Data sheet ( Hoja de datos )
| Número de pieza | 9ZX21200 | |
| Descripción | 12-OUTPUT DIFFERENTIAL Z-BUFFER | |
| Fabricantes | IDT | |
| Logotipo |  |
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12-OUTPUT DIFFERENTIAL Z-BUFFER FOR PCIE GEN3 AND QPI
DATASHEET
9ZX21200
Description
The 9ZX21200 is a small-footprint 12-output differential
buffer that meets all the performance requirements of the
Intel DB1200Z specification. The 9ZX21200 is backwards
compatible to PCIe Gen1 and Gen2 applications. A fixed,
internal feedback path maintains low drift for critical QPI
applications. In bypass mode, the 9ZX21200 can provide
outputs up to 150MHz.
Recommended Application
12-output PCIe Gen3/ QPI differential buffer for Romley and
newer platforms
Key Specifications
• Cycle-to-cycle jitter <50ps
• Output-to-output skew < 65 ps
• Input-to-output delay variation <50ps
• PCIe Gen3 phase jitter < 1.0ps RMS
• QPI 9.6GT/s 12UI phase jitter < 0.2ps RMS
Features/Benefits
• Space-saving 56-pin package
• Fixed feedback path for 0ps input-to-output delay
• 9 Selectable SMBus Addresses; Mulitple devices can
share the same SMBus Segment
• 4 OE# pins; Hardware control of four outputs
• PLL or bypass mode; PLL can dejitter incoming clock
• 100MHz or 133MHz PLL mode operation; supports PCIe
and QPI applications
• Selectable PLL bandwidth; minimizes jitter peaking in
downstream PLL's
• Spread Spectrum Compatible; tracks spreading input
clock for low EMI
• Software control of PLL Bandwidth and Bypass
Settings/PLL can dejitter incoming clock (B Rev only)
Output Features
• 12 - 0.7V differential HCSL output pairs
Block Diagram
OE(8,6,4,2)#
DIF_IN
DIF_IN#
Z-PLL
(SS Compatible)
DFB_OUT
DIF(11:0)
HIBW_BYPM_LOBW#
100M_133M#
CKPWRGD/PD#
SMB_A0_tri
SMB_A1_tri
SMBDAT
SMBCLK
Logic
IREF
IDT® 12-OUTPUT DIFFERENTIAL Z-BUFFER FOR PCIE GEN3 AND QPI
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9ZX21200
12-OUTPUT DIFFERENTIAL Z-BUFFER FOR PCIE GEN3 AND QPI
Electrical Characteristics–Input/Supply/Common Output Parameters
TA = TCOM; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN TYP
Ambient Operating
Temperature
Input High Voltage
Input Low Voltage
TCOM
VIH
VIL
IIN
Commmercial range
Single-ended inputs, except SMBus, low
threshold and tri-level inputs
Single-ended inputs, except SMBus, low
threshold and tri-level inputs
Single-ended inputs, VIN = GND, VIN = VDD
0
2
GND - 0.3
-5
Input Current
Single-ended inputs
IINP
VIN = 0 V; Inputs with internal pull-up resistors
-200
VIN = VDD; Inputs with internal pull-down resistors
Input Frequency
Pin Inductance
Capacitance
Fibyp
Fipll
Fipll
Lpin
CIN
CINDIF_IN
VDD = 3.3 V, Bypass mode
VDD = 3.3 V, 100MHz PLL mode
VDD = 3.3 V, 133.33MHz PLL mode
Logic Inputs, except DIF_IN
DIF_IN differential clock inputs
33
90 100.00
120 133.33
1.5
1.5
COUT
Output pin capacitance
Clk Stabilization
Input SS Modulation
Frequency
OE# Latency
TSTAB
fMODIN
tLATOE#
From VDD Power-Up and after input clock
stabilization or de-assertion of PD# to 1st clock
Allowable Frequency
(Triangular Modulation)
DIF start after OE# assertion
DIF stop after OE# deassertion
30
4
0.300
Tdrive_PD#
tDRVPD
DIF output enable after
PD# de-assertion
16
Tfall
Trise
SMBus Input Low Voltage
SMBus Input High Voltage
SMBus Output Low Voltage
SMBus Sink Current
Nominal Bus Voltage
SCLK/SDATA Rise Time
SCLK/SDATA Fall Time
SMBus Operating
Frequency
tF
tR
VILSMB
VIHSMB
VOLSMB
IPULLUP
VDDSMB
tRSMB
tFSMB
fMAXSMB
Fall time of control inputs
Rise time of control inputs
@ IPULLUP
@ VOL
3V to 5V +/- 10%
(Max VIL - 0.15) to (Min VIH + 0.15)
(Min VIH + 0.15) to (Max VIL - 0.15)
Maximum SMBus operating frequency
2.1
4
2.7
1Guaranteed by design and characterization, not 100% tested in production.
2Control input must be monotonic from 20% to 80% of input swing.
3Time from deassertion until outputs are >200 mV
4DIF_IN input
5The differential input clock must be running for the SMBus to be active
MAX
70
UNITS NOTES
°C 1
VDD + 0.3 V
0.8 V
5 uA
1
1
1
200 uA 1
150 MHz 2
110 MHz 2
147 MHz 2
7 nH 1
5 pF 1
2.7 pF 1,4
6 pF 1
1 ms 1,2
33 kHz 1
12 clocks 1,3
300
10
10
0.8
VDDSMB
0.4
5.5
1000
300
100
us
ns
ns
V
V
V
mA
V
ns
ns
kHz
1,3
1,2
1,2
1
1
1
1
1
1
1
1,5
IDT® 12-OUTPUT DIFFERENTIAL Z-BUFFER FOR PCIE GEN3 AND QPI
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9ZX21200
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9ZX21200
12-OUTPUT DIFFERENTIAL Z-BUFFER FOR PCIE GEN3 AND QPI
SMBusTable: PLL Mode, and Frequency Select Register
Byte 0 Pin #
Name
Control Function
Bit 7
3
PLL Mode 1
PLL Operating Mode Rd back 1
Bit 6
3
PLL Mode 0
PLL Operating Mode Rd back 0
Bit 5
Reserved
Bit 4
Reserved
Bit 3 These bits
PLL_SW_EN
Enable S/W control of PLL BW
Bit 2 available in B
PLL Mode 1
PLL Operating Mode 1
Bit 1 rev only.
PLL Mode 0
PLL Operating Mode 1
Bit 0
2
100M_133M#
Frequency Select Readback
SMBusTable: Output Control Register
Byte 1 Pin #
Name
Bit 7
42/41
DIF_7_En
Bit 6
38/37
DIF_6_En
Bit 5
34/35
DIF_5_En
Bit 4
30/29
DIF_4_En
Bit 3
25/26
DIF_3_En
Bit 2
23/24
DIF_2_En
Bit 1
18/19
DIF_1_En
Bit 0
16/17
DIF_0_En
Control Function
Output Control overrides OE# pin
Output Control overrides OE# pin
Output Control overrides OE# pin
Output Control overrides OE# pin
Output Control
Output Control
Output Control
Output Control
SMBusTable: Output Control Register
Byte 2 Pin #
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
55/54
DIF_11_En
Bit 2
53/52
DIF_10_En
Bit 1
48/47
DIF_9_En
Bit 0
46/45
DIF_8_En
Control Function
Reserved
Reserved
Reserved
Reserved
Output Control
Output Control
Output Control
Output Control
SMBusTable: Reserved Register
Byte 3 Pin #
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Control Function
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SMBusTable: Reserved Register
Byte 4 Pin #
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Control Function
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Type
R
R
RW
RW
RW
R
01
See PLL Operating Mode
Readback Table
HW Latch S/W Control
See PLL Operating Mode
Readback Table
133MHz
100MHz
Default
Latch
Latch
0
0
0
1
1
Latch
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
Low/Low
1
Enable
Default
1
1
1
1
1
1
1
1
Type
RW
RW
RW
RW
0
Low/Low
1
Enable
Default
0
0
0
0
1
1
1
1
Type
0
1 Default
0
0
0
0
0
0
0
0
Type
0
1 Default
0
0
0
0
0
0
0
0
IDT® 12-OUTPUT DIFFERENTIAL Z-BUFFER FOR PCIE GEN3 AND QPI
11
9ZX21200
REV D 041513
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet 9ZX21200.PDF ] | |
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