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PDF 9DMU0141 Data sheet ( Hoja de datos )

Número de pieza 9DMU0141
Descripción 2:1 1.5V PCIe Gen1-2-3 Clock Mux
Fabricantes IDT 
Logotipo IDT Logotipo



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2:1 1.5V PCIe Gen1-2-3 Clock Mux
w/Zo=100ohms
9DMU0141
DATASHEET
General Description
The 9DMU0141 is a member of IDT's SOC-Friendly 1.5V
Ultra-Low-Power (ULP) PCIe Gen1-2-3 family. It has
integrated output terminations providing Zo=100ohms for
direct connection to 100ohm transmission lines. The output
has an OE# pin for optimal system control and power
management. The part provides asynchronous or glitch-free
switching modes.
Recommended Application
2:1 1.5V PCIe Gen1-2-3 Clock Mux
Output Features
1 – Low-Power (LP) HCSL DIF pair w/Zo=100
Key Specifications
DIF additive cycle-to-cycle jitter <5ps
DIF phase jitter is PCIe Gen1-2-3 compliant
125MHz additive phase jitter 535fs rms typical (12kHz to
20MHz)
Features/Benefits
LP-HCSL output w/integrated terminations; saves 4
resistors compared to standard HCSL output
1.5V operation; 11mW typical power consumption
Selectable asynchronous or glitch-free switching; allows
the mux to be selected at power up even if both inputs are
not running, then transition to glitch-free switching mode
Spread Spectrum Compatible; supports EMI reduction
OE# pins; support DIF power management
HCSL differential inputs; can be driven by common clock
sources
1MHz to 167MHz operating frequency
Space saving 16-pin 3x3mm VFQFPN; minimal board
space
Block Diagram
^OE0#
DIF_INA
DIF_INB
vSW_MODE
^SEL_A_B#
A
DIF0
B
9DMU0141 REVISION A 09/30/14
1
©2014 Integrated Device Technology, Inc.

1 page




9DMU0141 pdf
9DMU0141 DATASHEET
Electrical Characteristics–Clock Input Parameters
TA = TAMB, Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
Input High Voltage - DIF_IN VIHDIF
Input Low Voltage - DIF_IN
Input Common Mode
Voltage - DIF_IN
VILDIF
VCOM
Differential inputs
(single-ended measurement)
Differential inputs
(single-ended measurement)
Common Mode Input Voltage
300
VSS - 300
200
Input Amplitude - DIF_IN
Input Slew Rate - DIF_IN
VSWING
dv/dt
Peak to Peak value (VIHDIF - VILDIF)
Measured differentially
300
0.35
Input Leakage Current
IIN
VIN = VDD , VIN = GND
Input Duty Cycle dtin Measurement from differential wavefrom
Input Jitter - Cycle to Cycle JDIFIn
Differential Measurement
1 Guaranteed by design and characterization, not 100% tested in production.
2 Slew rate measured through +/-75mV window centered around differential zero
-5
45
0
TYP
750
0
50
MAX
1150
UNITS NOTES
mV 1
300 mV 1
725
1450
8
5
55
150
mV
mV
V/ns
uA
%
ps
1
1
1,2
1
1
Electrical Characteristics–DIF Low-Power HCSL Outputs
TA = TAMB, Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS NOTES
Slew rate
Slew rate matching
dV/dt
ΔdV/dt
Scope averaging on, fast setting
Slew rate matching, Scope averaging on
1.2 2.4 3.6 V/ns 1,2,3
13 20 % 1,2,4
Voltage High
Voltage Low
VHIGH
VLOW
Statistical measurement on single-ended signal 550 755 850
using oscilloscope math function. (Scope
mV
averaging on)
-150 21 150
Max Voltage
Min Voltage
Vmax
Vmin
Measurement on single ended signal using
absolute value. (Scope averaging off)
766 1150 mV
-300 -25
Vswing
Vswing
Scope averaging off
300 1469
mV 1,2
Crossing Voltage (abs) Vcross_abs
Scope averaging off
250 367 550 mV 1,5
Crossing Voltage (var)
Δ-Vcross
Scope averaging off
12 140 mV 1,6
1Guaranteed by design and characterization, not 100% tested in production.
2 Measured from differential waveform
3 Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around
differential 0V.
4 Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on
the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the
oscilloscope is to use for the edge rate calculations.
5 Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising
edge (i.e. Clock rising and Clock# falling).
6 The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross
absolute) allowed. The intent is to limit Vcross induced modulation by setting Δ-Vcross to be smaller than Vcross absolute.
Electrical Characteristics–Current Consumption
TA = TAMB, Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
Operating Supply Current
IDD
VDD, All outputs active @100MHz
Powerdown Current
IDDPD
VDD, all outputs disabled
1 Guaranteed by design and characterization, not 100% tested in production.
2 Input clock stopped.
TYP
7
1.4
MAX
11
2.5
UNITS
mA
mA
NOTES
1
1, 2
REVISION A 09/30/14
5 2:1 1.5V PCIE GEN1-2-3 CLOCK MUX W/ZO=100OHMS

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