PDF ICS932S431A Data sheet ( Hoja de datos )

Número de pieza	ICS932S431A
Descripción	PCIe Gen 2 and QPI Clock
Fabricantes	Integrated Circuit Systems
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ICS932S431A Datasheet PCIe Gen 2 and QPI Clock for Intel-based Servers Recommended Application: PCIe Gen 2 & QPI compliant CK410B (CK410B+) clock for Intel-based servers Output Features: • 4 - 0.7V current-mode differential CPU pairs • 5 - 0.7V current-mode differential SRC pair • 4 - PCI (33MHz) • 3 - PCICLK_F, (33MHz) free-running • 1 - 48MHz • 2 - REF, 14.318MHz Key Specifications: • Low drift PCIe clocks for Non-Transparent Bridging (NTB) • PCIe Gen 2 compliant SRC outputs • QPI & FBD compliant CPU clocks • CPU cycle-cycle jitter: < 50ps • SRC cycle-cycle jitter: < 125ps • PCI cycle-cycle jitter: < 500ps • CPU output skew: < 50ps • SRC output skew: < 250ps • ± 100ppm frequency accuracy on all outputs Features/Benefits: • Supports spread spectrum modulation, 0 to -0.5% down spread on CPU outputs • Uses external 14.318MHz crystal and external load capacitors for low ppm synthesis error • CPU clocks independent of SRC/PCI clocks • D2/D3 SMBus address Functionality FS_C1 0 0 0 0 1 1 1 1 FS_B1 0 0 1 1 0 0 1 1 FS_A2 0 1 0 1 0 1 0 1 CPU MHz 266.67 133.33 200.00 166.67 333.33 100.00 400.00 N/A SRC MHz 100.00 PCI MHz 33.33 REF MHz 14.32 USB MHz 48.00 1. FS_B and FS_C are three-level inputs. Please see VIL_FS and VIH_FS specifications in the Input/Supply/Common Output Parameters Table for correct values. Also refer to the Test Clarification Table. 2. FS_A is a low-threshold input. Please see the VIL_FS and VIH_FS specifications in the Input/Supply/Common Output Parameters Table for correct values. 1426A—11/12/09 Pin Configuration VDDPCI 1 GNDPCI 2 PCICLK0 3 PCICLK1 4 PCICLK2 5 PCICLK3 6 GNDPCI 7 VDDPCI 8 PCICLK_F0 9 PCICLK_F1 10 PCICLK_F2 11 VDD48 12 48MHz 13 GND48 14 VDDSRC 15 SRCCLKT0 16 SRCCLKC0 17 SRCCLKC1 18 SRCCLKT1 19 GNDSRC 20 SRCCLKT2 21 SRCCLKC2 22 SRCCLKC3 23 SRCCLKT3 24 VDDSRC 25 SRCCLKT4 26 SRCCLKC4 27 VDDSRC 28 56 FS_C/TEST_SEL 55 REF0 54 REF1 53 VDDREF 52 X1 51 X2 50 GNDREF 49 FS_B/TEST_MODE 48 FS_A 47 VDDCPU 46 CPUCLKT0 45 CPUCLKC0 44 VDDCPU 43 CPUCLKT1 42 CPUCLKC1 41 GNDCPU 40 CPUCLKT2 39 CPUCLKC2 38 VDDCPU 37 CPUCLKT3 36 CPUCLKC3 35 VDDA 34 GNDA 33 IREF 32 NC 31 Vtt_PwrGd#/PD 30 SDATA 29 SCLK 56-pin TSSOP ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals. IDT reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners. 1 page Integrated Circuit Systems, Inc. ICS932S431A Datasheet Absolute Maximum Rating PARAMETER SYMBOL 3.3V Core Supply Voltage VDD_A 3.3V Logic Input Supply Voltage Storage Temperature Ambient Operating Temp Case Temperature VDD_In Ts Tambient Tcase Input ESD protection HBM ESD prot CONDITIONS - - - - - - MIN TYP MAX UNITS Notes VDD + 0.5V V 1 GND - 0.5 -65 0 2000 VDD + 0.5V 150 70 115 V °C °C °C V 1 1 1 1 1 1Guaranteed by design and characterization, not 100% tested in production. Electrical Characteristics - Input/Supply/Common Output Parameters PARAMETER SYMBOL CONDITIONS* MIN TYP MAX UNITS Input High Voltage Input Low Voltage Input High Current Input Low Current Low Threshold Input- High Voltage Low Threshold Input- Low Voltage VIH 3.3 V +/-5% 2 VIL 3.3 V +/-5% VSS - 0.3 IIH VIN = VDD -5 IIL1 VIN = 0 V; Inputs with no pull-up resistors -5 IIL2 VIN = 0 V; Inputs with pull-up resistors -200 VIH_FS 3.3 V +/-5% 0.7 VIL_FS 3.3 V +/-5% VSS - 0.3 VDD + 0.3 0.8 5 V V uA uA uA VDD + 0.3 0.35 V V Operating Supply Current Powerdown Current IDD3.3OP IDD3.3PD Full Active, CL = Full load; all diff pairs driven all differential pairs tri-stated 350 mA 70 mA 12 mA Input Frequency Pin Inductance Input Capacitance Clk Stabilization Modulation Frequency Tdrive_PD Tfall_PD Trise_PD Fi Lpin CIN COUT CINX TSTAB VDD = 3.3 V Logic Inputs Output pin capacitance X1 & X2 pins From VDD Power-Up or de- assertion of PD to 1st clock Triangular Modulation CPU output enable after PD de-assertion PD fall time of PD rise time of 14.31818 7 5 6 5 1.8 30 33 300 5 5 MHz nH pF pF pF ms kHz us ns ns SMBus Voltage VDD 2.7 5.5 V Low-level Output Voltage VOL @ IPULLUP 0.4 V Current sinking at VOL = 0.4 V IPULLUP 4 mA SCLK/SDATA Clock/Data Rise Time TRI2C (Max VIL - 0.15) to (Min VIH + 0.15) 1000 ns SCLK/SDATA Clock/Data Fall Time TFI2C (Min VIH + 0.15) to (Max VIL - 0.15) 300 ns *TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5% 1Guaranteed by design and characterization, not 100% tested in production. 2 Input frequency should be measured at the REF pin and tuned to ideal 14.31818MHz to meet ppm frequency accuracy on PLL outputs. Notes 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1426A—11/12/09 5 5 Page Integrated Circuit Systems, Inc. ICS932S431A Datasheet General SMBus serial interface information for the ICS932S431A How to Write: • Controller (host) sends a start bit. • Controller (host) sends the write address D2 (H) • ICS clock will acknowledge • Controller (host) sends the begining byte location = N • ICS clock will acknowledge • Controller (host) sends the data byte count = X • ICS clock will acknowledge • Controller (host) starts sending Byte N through Byte N + X -1 (see Note 2) • ICS clock will acknowledge each byte one at a time • Controller (host) sends a Stop bit How to Read: • Controller (host) will send start bit. • Controller (host) sends the write address D2 (H) • ICS clock will acknowledge • Controller (host) sends the begining byte location = N • ICS clock will acknowledge • Controller (host) will send a separate start bit. • Controller (host) sends the read address D3 (H) • ICS clock will acknowledge • ICS clock will send the data byte count = X • ICS clock sends Byte N + X -1 • ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). • Controller (host) will need to acknowledge each byte • Controllor (host) will send a not acknowledge bit • Controller (host) will send a stop bit Index Block Write Operation Controller (Host) T starT bit ICS (Slave/Receiver) Slave Address D2(H) WR WRite Beginning Byte = N Data Byte Count = X Beginning Byte N ACK ACK ACK ACK Byte N + X - 1 P stoP bit ACK 1426A—11/12/09 11 Index Block Read Operation Controller (Host) T starT bit ICS (Slave/Receiver) Slave Address D2(H) WR WRite Beginning Byte = N RT Repeat starT ACK ACK Slave Address D3(H) RD ReaD ACK ACK ACK Data Byte Count = X Beginning Byte N N Not acknowledge P stoP bit Byte N + X - 1 11 Page

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