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PDF ICS932S208 Data sheet ( Hoja de datos )
| Número de pieza | ICS932S208 | |
| Descripción | Programmable Timing Control Hub | |
| Fabricantes | IDT | |
| Logotipo |  |
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DATASHEET
PGreongrPa4mTMmaPbrloeceTsimsoinr g Control HubTM for Next
ICS932S208
Recommended Application:
CK409B clock, Intel Yellow Cover part, Server Applications
Output Features:
• 4 - 0.7V current-mode differential CPU pairs
• 1 - 0.7V current-mode differential SRC pair
• 7 - PCI (33MHz)
• 3 - PCICLK_F, (33MHz) free-running
• 1 - USB, 48MHz
• 1 - DOT, 48MHz
• 2 - REF, 14.318MHz
• 4 - 3V66, 66.66MHz
• 1 - VCH/3V66, selectable 48MHz or 66MHz
Key Specifications:
• CPU/SRC outputs cycle-cycle jitter < 125ps
• 3V66 outputs cycle-cycle jitter < 250ps
• PCI outputs cycle-cycle jitter < 250ps
• CPU outputs skew: < 100ps
• +/- 300ppm frequency accuracy on CPU & SRC clocks
Functionality
CPU
B6b5 FS_A FS_B MHz
0 0 100
0 MID Ref/N0
0 0 1 200
1 0 133
1 1 166
1 MID Hi-Z
0 0 200
1
0
1
1 400
0 266
1 1 333
SRC
MHz
100/200
Ref/N1
100/200
100/200
100/200
Hi-Z
100/200
100/200
100/200
100/200
3V66 PCI
MHz MHz
66.66 33.33
Ref/N2 Ref/N3
66.66 33.33
66.66 33.33
66.66 33.33
Hi-Z Hi-Z
66.66 33.33
66.66 33.33
66.66 33.33
66.66 33.33
REF
MHz
14.318
Ref/N4
14.318
14.318
14.318
Hi-Z
14.318
14.318
14.318
14.318
USB/DOT
MHz
48.00
Ref/N5
48.00
48.00
48.00
Hi-Z
48.00
48.00
48.00
48.00
Features/Benefits:
• Supports tight ppm accuracy clocks for Serial-ATA
• Supports spread spectrum modulation, 0 to -0.5%
down spread and +/- 0.25% center spread
• Supports CPU clks up to 400MHz in test mode
• Uses external 14.318MHz crystal
Pin Configuration
REF0 1
REF1 2
VDDREF 3
X1 4
X2 5
GND 6
PCICLK_F0 7
PCICLK_F1 8
PCICLK_F2 9
VDDPCI 10
GND 11
PCICLK0 12
PCICLK1 13
PCICLK2 14
PCICLK3 15
VDDPCI 16
GND 17
PCICLK4 18
PCICLK5 19
PCICLK6 20
PD# 21
3V66_0 22
3V66_1 23
VDD3V66 24
GND 25
3V66_2 26
3V66_3 27
SCLK 28
56 FS_B
55 VDDA
54 GNDA
53 GND
52 IREF
51 FS_A
50 CPUCLKT3
49 CPUCLKC3
48 VDDCPU
47 CPUCLKT2
46 CPUCLKC2
45 GND
44 CPUCLKT1
43 CPUCLKC1
42 VDDCPU
41 CPUCLKT0
40 CPUCLKC0
39 GND
38 SRCCLKT
37 SRCCLKC
36 VDD
35 Vtt_PWRGD#
34 VDD48
33 GND
32 48MHz_DOT
31 48MHz_USB
30 SDATA
29 3V66_4/VCH
56-pin SSOP & TSSOP
IDTTM Programmable Timing Control HubTM for Next Gen P4TM Processor
1
0743G—01/26/10
1 page  
ICS932S208
Programmable Timing Control HubTM for Next Gen P4TM Processor
Absolute Maximum Ratings
Symbol
VDD_A
VDD_In
Ts
Tambient
Tcase
ESD prot
Parameter
3.3V Core Supply Voltage
3.3V Logic Input Supply Voltage
Storage Temperature
Ambient Operating Temp
Case Temperature
Input ESD protection
human body model
Min
GND - 0.5
-65
0
2000
Max
VDD + 0.5V
VDD + 0.5V
150
70
115
Units
V
V
°C
°C
°C
V
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN TYP
Input High Voltage
Input MID Voltage
Input Low Voltage
Input High Current
Input Low Current
VIH
VMID
VIL
IIH
IIL1
IIL2
3.3 V +/-5%
3.3 V +/-5%
3.3 V +/-5%
VIN = VDD
VIN = 0 V; Inputs with no pull-up
resistors
VIN = 0 V; Inputs with pull-up
resistors
2
1
VSS - 0.3
-5
-5
-200
MAX
VDD + 0.3
1.8
0.8
5
UNITS NOTES
V
V
V
uA
uA
uA
Operating Supply Current IDD3.3OP
Full Active, CL = Full load;
350
Powerdown Current
IDD3.3PD
all diff pairs driven
all differential pairs tri-stated
35
12
Input Frequency3
Pin Inductance1
Fi
Lpin
VDD = 3.3 V
14.31818
7
Input Capacitance1
CIN
COUT
Logic Inputs
Output pin capacitance
5
6
Clk Stabilization1,2
CINX
TSTAB
X1 & X2 pins
From VDD Power-Up or de-
assertion of PD# to 1st clock
5
1.8
Modulation Frequency
Triangular Modulation
30
33
Tdrive_SRC
SRC output enable after
PCI_Stop# de-assertion
15
Tdrive_PD#
CPU output enable after
PD# de-assertion
300
Tfall_Pd#
PD# fall time of
5
Trise_Pd#
PD# rise time of
5
Tdrive_CPU_Stop#
CPU output enable after
CPU_Stop# de-assertion
10
Tfall_CPU_Stop#
PD# fall time of
5
Trise_CPU_Stop#
PD# rise time of
5
1Guaranteed by design, not 100% tested in production.
2See timing diagrams for timing requirements.
3 Input frequency should be measured at the REF output pin and tuned to ideal 14.31818MHz to meet
ppm frequency accuracy on PLL outputs.
mA
mA
mA
MHz
nH
pF
pF
pF
ms
kHz
ns
us
ns
ns
us
ns
ns
3
1
1
1
1
1,2
1
1
1
1
2
1
1
2
IDTTM Programmable Timing Control HubTM for Next Gen P4TM Processor
5
0743G—01/26/10
5 Page 
ICS932S208
Programmable Timing Control HubTM for Next Gen P4TM Processor
General I2C serial interface information for the ICS932S208
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2 (H)
• ICS clock will acknowledge
• Controller (host) sends the begining byte location = N
• ICS clock will acknowledge
• Controller (host) sends the data byte count = X
• ICS clock will acknowledge
• Controller (host) starts sending Byte N through
Byte N + X -1
(see Note 2)
• ICS clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the write address D2 (H)
• ICS clock will acknowledge
• Controller (host) sends the begining byte
location = N
• ICS clock will acknowledge
• Controller (host) will send a separate start bit.
• Controller (host) sends the read address D3 (H)
• ICS clock will acknowledge
• ICS clock will send the data byte count = X
• ICS clock sends Byte N + X -1
• ICS clock sends Byte 0 through byte X (if X(H)
was written to byte 8).
• Controller (host) will need to acknowledge each byte
• Controllor (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host)
ICS (Slave/Receiver)
T starT bit
Slave Address D2(H)
WR WRite
ACK
Beginning Byte = N
ACK
Data Byte Count = X
ACK
Beginning Byte N
ACK
Byte N + X - 1
P stoP bit
ACK
Index Block Read Operation
Controller (Host)
ICS (Slave/Receiver)
T starT bit
Slave Address D2(H)
WR WRite
ACK
Beginning Byte = N
ACK
RT Repeat starT
Slave Address D3(H)
RD ReaD
ACK
ACK
ACK
Data Byte Count = X
Beginning Byte N
N Not acknowledge
P stoP bit
Byte N + X - 1
IDTTM Programmable Timing Control HubTM for Next Gen P4TM Processor
11
0743G—01/26/10
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet ICS932S208.PDF ] | |
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