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PDF 853S058 Data sheet ( Hoja de datos )
| Número de pieza | 853S058 | |
| Descripción | LVPECL/ECL Clock Multiplexer | |
| Fabricantes | IDT | |
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8:1 Differential-to-3.3V or 2.5V
LVPECL/ECL Clock Multiplexer
853S058
DATA SHEET
General Description
The 853S058 is an 8:1 Differential-to-3.3V or 2.5V LVPECL / ECL
Clock Multiplexer which can operate up to 2.5 GHz. The 853S058
has 8 differential selectable clock inputs. The PCLK, nPCLK input
pairs can accept LVPECL, LVDS, SSTL or CML levels. The fully
differential architecture and low propagation delay make it ideal for
use in clock distribution circuits. The select pins have internal
pulldown resistors. The SEL2 pin is the most significant bit and the
binary number applied to the select pins will select the same
numbered data input (i.e., 000 selects PCLK0, nPCLK0).
Block Diagram
PCLK0 Pulldown
nPCLK0 Pullup/Pulldown
PCLK1 Pulldown
nPCLK1 Pullup/Pulldown
PCLK2 Pulldown
nPCLK2 Pullup/Pulldown
PCLK3 Pulldown
nPCLK3 Pullup/Pulldown
PCLK4 Pulldown
nPCLK4 Pullup/Pulldown
PCLK5 Pulldown
nPCLK5 Pullup/Pulldown
PCLK6 Pulldown
nPCLK6 Pullup/Pulldown
PCLK7 Pulldown
nPCLK7 Pullup/Pulldown
000
(default)
001
010
011
100
101
110
111
Q
nQ
Features
• High speed 8:1 differential muliplexer
• One differential 3.3V or 2.5V LVPECL output pair
• Eight selectable differential PCLKx, nPCLKx input pairs
• Differential PCLKx, nPCLKx pairs can accept the following
interface levels: LVPECL, LVDS, SSTL,CML
• Maximum output frequency: 2.5GHz
• Translates any single ended input signal to LVPECL levels with
resistor bias on nPCLKx input
• Additive phase jitter, RMS: 0.075ps (typical)
• Part-to-part skew: 350ps (maximum)
• Propagation delay: 600ps (maximum)
• LVPECL mode operating voltage supply range:
VCC = 2.375V to 3.465V, VEE = 0V
• ECL mode operating voltage supply range:
VCC = 0V, VEE = -3.465V to -2.375V
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package
Pin Assignment
PCLK0
nPCLK0
PCLK1
nPCLK1
VCC
SEL0
SEL1
SEL2
PCLK2
nPCLK2
PCLK3
nPCLK3
1
2
3
4
5
6
7
8
9
10
11
12
24 PCLK7
23 nPCLK7
22 PCLK6
21 nPCLK6
20 VCC
19 Q
18 nQ
17 VEE
16 PCLK5
15 nPCLK5
14 PCLK4
13 nPCLK4
853S058
24-Lead TSSOP, 173-MIL
4.4mm x 7.8mm x 0.925mm
package body
G Package
Top View
SEL2 Pulldown
SEL1 Pulldown
SEL0 Pulldown
853S058 REVISION B 1/6/15
1 ©2015 Integrated Device Technology, Inc.
1 page  
853S058 DATA SHEET
AC Electrical Characteristics
Table 5. AC Characteristics, VCC = 0V, VEE = -3.465V to -2.375V or VCC = 2.375 to 3.465V, VEE = 0V, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum Units
fOUT
tjit
Output Frequency
Buffer Additive Phase Jitter,
RMS; refer to Additive Phase
Jitter section
155.52MHz, Integration Range:
12kHz – 20MHz
0.075
2.5 GHz
ps
tPD
Propagation Delay;
NOTE 1
250 600 ps
tsk(pp)
Part-to-Part Skew;
NOTE 2, 3
350 ps
tsk(i)
Input Skew
75 ps
tR / tF
Output Rise/Fall Time
MUXISOLATION MUX Isolation; NOTE 4
20% to 80%
155.52MHz,
Input Peak-to-Peak = 800mV
75
250 ps
90 dB
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE: All parameters measured 1.0GHz, unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions. Using the
same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 3: This parameter is defined according with JEDEC Standard 65.
NOTE 4: Q, nQ output measured differentially. See Parameter Measurement Information for MUX Isolation diagram.
REVISION B 1/6/15
5 8:1 DIFFERENTIAL-TO-3.3V OR 2.5V LVPECL/ECL
CLOCK MULTIPLEXER
5 Page 
853S058 DATA SHEET
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
The differential outputs are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50
transmission lines. Matched impedance techniques should be used
to maximize operating frequency and minimize signal distortion.
Figures 3A and 3B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts may
exist and it would be recommended that the board designers
simulate to guarantee compatibility across all printed circuit and clock
component process variations.
3.3V
LVPECL
3.3V
R3 R4
125Ω
125Ω
3.3V
Zo = 50Ω
+
Zo = 50Ω
R1
84Ω
_
R2
84Ω
Input
Figure 3A. 3.3V LVPECL Output Termination
Figure 3B. 3.3V LVPECL Output Termination
REVISION B 1/6/15
11 8:1 DIFFERENTIAL-TO-3.3V OR 2.5V LVPECL/ECL
CLOCK MULTIPLEXER
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet 853S058.PDF ] | |
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