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PDF ICS853S54I Data sheet ( Hoja de datos )
| Número de pieza | ICS853S54I | |
| Descripción | Differential-to-LVPECL/ECL Multiplexer | |
| Fabricantes | IDT | |
| Logotipo |  |
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Dual 2:1, 1:2 Differential-to-LVPECL/ECL
Multiplexer
ICS853S54I
DATA SHEET
General Description
The ICS853S54I is a dual 2:1 and 1:2 Multiplexer. The 2:1 Multiplex-
er allows one of 2 inputs to be selected onto one output pin and the
1:2 MUX switches one input to one of two outputs. This device is
useful for multiplexing multi-rate Ethernet PHYs which have 100 M
bit and 1000 bit transmit/receive pairs onto an optical SFP module
which has a single transmit/receive pair. See Application Section for
further information.
The ICS853S54I is optimized for applications requiring very high
performance and has a maximum operating frequency of 2.5GHz.
The device is packaged in a small, 3mm x 3mm VFQFN package,
making it ideal for use on space-constrained boards.
Features
• Three differential LVPECL output pairs
• Three differential LVPECL clock inputs
• PCLKx/nPCLKx pairs can accept the following differential input
levels: LVPECL, LVDS, CML
• Maximum output frequency: 2.5GHz
• Part-to-part skew: 200ps (maximum)
• Propagation delay: QA, nQA: 450ps (maximum)
QBx, nQBx: 420ps (maximum)
• LVPECL mode operating voltage supply range:
VCC = 2.375V to 3.465V, VEE = 0V
• ECL mode operating voltage supply range:
VCC = 0V, VEE = -3.465V to -2.375V
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) packageing
Block Diagram
CLK_SELA Pulldown
PCLKA0 Pulldown
nPCLKA0 Pullup/Pulldown
PCLKA1 Pulldown
nPCLKA1 Pullup/Pulldown
PCLKB Pulldown
nPCLKB Pullup/Pulldown
CLK_SELB Pulldown
0
QA
nQA
1
QB0
nQB0
QB1
nQB1
Pin Assignment
16 15 14 13
QB0 1
12 PCLKA0
nQB0 2
11 nPCLKA0
QB1 3
10 PCLKA1
nQB1 4
9 nPCLKA1
5 6 78
ICS853S54I
16-Lead VFQFN
3mm x 3mm x 0.925mm package body
K Package
Top View
ICS853S54AKI REVISION A OCTOBER 30, 2012
1
©2012 Integrated Device Technology, Inc.
1 page  
ICS853S54I Data Sheet
DUAL 2:1, 1:2 DIFFERENTIAL-TO-LVPECL/ECL MULTIPLEXER
Additive Phase Jitter
The spectral purity in a band at a specific offset from the fundamental
compared to the power of the fundamental is called the dBc Phase
Noise. This value is normally expressed using a Phase noise plot
and is most often the specified plot in many applications. Phase noise
is defined as the ratio of the noise power present in a 1Hz band at a
specified offset from the fundamental frequency to the power value
of the fundamental. This ratio is expressed in decibels (dBm) or a
ratio of the power in the 1Hz band to the power in the fundamental.
When the required offset is specified, the phase noise is called a dBc
value, which simply means dBm at a specified offset from the
fundamental. By investigating jitter in the frequency domain, we get
a better understanding of its effects on the desired application over
the entire time record of the signal. It is mathematically possible to
calculate an expected bit error rate given a phase noise plot.
Additive Phase Jitter @ 622.08MHz
12kHz to 20MHz = 0.035ps (typical)
Offset from Carrier Frequency (Hz)
As with most timing specifications, phase noise measurements has
issues relating to the limitations of the equipment. Often the noise
floor of the equipment is higher than the noise floor of the device. This
is illustrated above. The device meets the noise floor of what is
shown, but can actually be lower. The phase noise is dependent on
the input source and measurement equipment.
The source generator "IFR2042 10kHz – 56.4GHz Low Noise Signal
Generator as external input to an Agilent 8133A 3GHz Pulse
Generator".
ICS853S54AKI REVISION A OCTOBER 30, 2012
5
©2012 Integrated Device Technology, Inc.
5 Page 
ICS853S54I Data Sheet
DUAL 2:1, 1:2 DIFFERENTIAL-TO-LVPECL/ECL MULTIPLEXER
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
The differential outputs are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50
transmission lines. Matched impedance techniques should be used
to maximize operating frequency and minimize signal distortion.
Figures 5A and 5B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts may
exist and it would be recommended that the board designers
simulate to guarantee compatibility across all printed circuit and clock
component process variations.
3.3V
Zo = 50Ω
3.3V
+
LVPECL
Zo = 50Ω
R1
50Ω
RTT =
1
((VOH + VOL) / (VCC – 2)) – 2
* Zo
_
Input
R2
50Ω
VCC - 2V
RTT
Figure 5A. 3.3V LVPECL Output Termination
3.3V
LVPECL
3.3V
R3 R4
125Ω
125Ω
3.3V
Zo = 50Ω
+
Zo = 50Ω
R1
84Ω
_
R2
84Ω
Input
Figure 5B. 3.3V LVPECL Output Termination
ICS853S54AKI REVISION A OCTOBER 30, 2012
11
©2012 Integrated Device Technology, Inc.
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet ICS853S54I.PDF ] | |
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