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PDF ICS853S12I Data sheet ( Hoja de datos )
| Número de pieza | ICS853S12I | |
| Descripción | LVPECL FANOUT BUFFER | |
| Fabricantes | IDT | |
| Logotipo |  |
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LOW SKEW, 1-TO-12, DIFFERENTIAL-TO-
3.3V, 2.5V LVPECL FANOUT BUFFER
ICS853S12I
GENERAL DESCRIPTION
The ICS853S12I is a low skew, 1-to-12 Differential-
ICS to-3.3V, 2.5V LVPECL Fanout Buffer and a member
HiPerClockS™ of the HiPerClockS™ family of High Performance
Clock Solutions from IDT. The PCLK, nPCLK pair
accepts LVPECL, CML, and SSTL differential input
levels. The high gain differential amplifier accepts peak-to-peak
input voltages as small as 150mV, as long as the common mode
voltage is within the specified minimum and maximum range.
Guaranteed output and part-to-part skew characteristics make
the ICS853S12I ideal for those clock distribution applications
demanding well defined performance and repeatability.
FEATURES
• Twelve differential 3.3V, 2.5V LVPECL outputs
• PCLK, nPCLK input pair
• PCLK, nPCLK pair can accept the following differential
input levels: LVPECL, CML, SSTL
• Maximum output frequency: 1.5GHz
• Translates any single-ended input signal to 2.5V or 3.3V
LVPECL levels with a resistor bias on nPCLK input
• Additive phase jitter, RMS: 0.06ps (typical)
• Output skew: 50ps (maximum)
• Part-to-part skew: 250ps (maximum)
• Propagation delay: 680ps (maximum)
• Full 3.3V or 2.5V operating supply modes
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package
BLOCK DIAGRAM
PCLK Pulldown
nPCLK Pullup/Pulldown
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
Q11
nQ11
Q10
nQ10
Q9
nQ9
Q8
nQ8
Q7
nQ7
Q6
nQ6
PIN ASSIGNMENT
Q11
nQ11
VEE
PCLK
nPCLK
VEE
Q0
nQ0
32 31 30 29 28 27 26 25
1 24
2 23
3 ICS853S12I 22
4 32-Lead VFQFN 21
5 5mm x 5mm x 0.925mm 20
package body
6 K Package 19
7 Top View 18
8 17
9 10 11 12 13 14 15 16
nQ7
Q7
nQ6
Q6
nQ5
Q5
nQ4
Q4
IDT™ / ICS™ LVPECL FANOUT BUFFER
1
ICS853S12AKI REV. A MAY 21, 2008
1 page  
ICS853S12I
LOW SKEW, 1-TO-12, DIFFERENTIAL-TO-3.3V, 2.5V LVPECL FANOUT BUFFER
ADDITIVE PHASE JITTER
The spectral purity in a band at a specific offset from the
fundamental compared to the power of the fundamental is called
the dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise power
present in a 1Hz band at a specified offset from the fundamental
frequency to the power value of the fundamental. This ratio is
expressed in decibels (dBm) or a ratio of the power in the 1Hz
band to the power in the fundamental. When the required offset
is specified, the phase noise is called a dBc value, which simply
means dBm at a specified offset from the fundamental. By
investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the
entire time record of the signal. It is mathematically possible to
calculate an expected bit error rate given a phase noise plot.
Additive Phase Jitter
622MHz (12kHz to 20MHz) = 0.06ps typical
OFFSET FROM CARRIER FREQUENCY (HZ)
As with most timing specifications, phase noise measurements
has issues relating to the limitations of the equipment. Often the
noise floor of the equipment is higher than the noise floor of the
device. This is illustrated above. The device meets the noise floor
of what is shown, but can actually be lower. The phase noise is
dependent on the input source and measurement equipment.
IDT™ / ICS™ LVPECL FANOUT BUFFER 5 ICS853S12AKI REV. A MAY 21, 2008
5 Page 
ICS853S12I
LOW SKEW, 1-TO-12, DIFFERENTIAL-TO-3.3V, 2.5V LVPECL FANOUT BUFFER
TERMINATION FOR 2.5V LVPECL OUTPUTS
Figure 5A and Figure 5B show examples of termination for 2.5V
LVPECL driver. These terminations are equivalent to terminating
50Ω to V - 2V. For V = 2.5V, the V - 2V is very close to ground
CC CC
CC
level. The R3 in Figure 5B can be eliminated and the termination
is shown in Figure 5C.
VC C=2. 5V
Zo = 50 Ohm
Zo = 50 Ohm
2,5V LVPECL
Driv er
2. 5V
R1 R3
250 250
2.5V
+
-
R2
62. 5
R4
62. 5
VCC=2.5V
Zo = 50 Ohm
Zo = 50 Ohm
2,5V LVPECL
Driv er
2. 5V
+
-
R1 R2
50 50
R3
18
FIGURE 5A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 5B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
VC C=2. 5V
Zo = 50 Ohm
Zo = 50 Ohm
2,5V LVPECL
Driv er
2.5V
+
-
R1 R2
50 50
FIGURE 5C. 2.5V LVPECL TERMINATION EXAMPLE
IDT™ / ICS™ LVPECL FANOUT BUFFER
11
ICS853S12AKI REV. A MAY 21, 2008
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet ICS853S12I.PDF ] | |
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