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PDF ICS853S057I Data sheet ( Hoja de datos )

Número de pieza ICS853S057I
Descripción LVPECL/ECL Clock Data Multiplexer
Fabricantes IDT 
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4:1, Differential-To-3.3V, 2.5V LVPECL/ECL
Clock Data Multiplexer
ICS853S057I
DATA SHEET
General Description
The ICS853S057I is a 4:1 Differential-to-3.3V or 2.5V LVPECL/ECL
Clock/Data Multiplexer which can operate up to 3GHz. The
ICS853S057I has 4 differential selectable clock input pairs. The
CLK, nCLK input pairs can accept LVPECL, LVDS, CML or SSTL
levels. The fully differential architecture and low propagation delay
make it ideal for use in clock distribution circuits. The multiplexer
select control inputs have ECL/LVPECL interface levels. The select
pins have internal pulldown resistors.
Features
High speed 4:1 differential muliplexer
One differential 3.3V, 2.5V LVPECL/ECL output
Four differential CLKx, nCLKx input pairs
Differential CLKx, nCLKx pairs can accept the following interface
levels: LVPECL, LVDS, CML, SSTL
Maximum input/output frequency: 3GHz
Additive phase jitter, RMS @ 622.08MHz: 0.073ps (typical)
Part-to-part skew: 250ps (maximum)
Propagation delay: 615ps (maximum)
LVPECL mode operating voltage supply range:
VCC = 2.375V to 3.465V, VEE = 0V
ECL mode operating voltage supply range:
VCC = 0V, VEE = -3.465V to -2.375V
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) packages
Block Diagram
CLK0 Pulldown
nCLK0 Pulldown
CLK1 Pulldown
nCLK1 Pulldown
CLK2 Pulldown
nCLK2 Pulldown
CLK3 Pulldown
nCLK3 Pulldown
SEL1 Pulldown
SEL0 Pulldown
VBB1
VBB2
00
(default)
01
10
11
Q
nQ
Pin Assignment
VCC
CLK0
nCLK0
CLK1
nCLK1
CLK2
nCLK2
CLK3
nCLK3
VEE
1
2
3
4
5
6
7
8
9
10
20 VCC
19 SEL1
18 SEL0
17 VCC
16 Q
15 nQ
14 VCC
13 VBB1
12 VBB2
11 VEE
ICS853S057I
20-Lead TSSOP
6.5mm x 4.4mm x 0.925mm
package body
G Package
Top View
ICS853S057AGI REVISION A MAY 16, 2012
1
©2012 Integrated Device Technology, Inc.

1 page




ICS853S057I pdf
ICS853S057I Data Sheet
4:1, DIFFERENTIAL-TO-3.3V, 2.5V LVPECL/ECL CLOCK DATA MULTIPLEXER
Additive Phase Jitter
The spectral purity in a band at a specific offset from the fundamental
compared to the power of the fundamental is called the dBc Phase
Noise. This value is normally expressed using a Phase noise plot
and is most often the specified plot in many applications. Phase noise
is defined as the ratio of the noise power present in a 1Hz band at a
specified offset from the fundamental frequency to the power value of
the fundamental. This ratio is expressed in decibels (dBm) or a ratio
of the power in the 1Hz band to the power in the fundamental. When
the required offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the fundamental.
By investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the entire
time record of the signal. It is mathematically possible to calculate an
expected bit error rate given a phase noise plot.
Additive Phase Jitter @ 622.08MHz
12kHz to 20MHz = 0.073ps (typical)
Offset from Carrier Frequency (Hz)
As with most timing specifications, phase noise measurements has
issues relating to the limitations of the equipment. Often the noise
floor of the equipment is higher than the noise floor of the device. This
is illustrated above. The device meets the noise floor of what is
shown, but can actually be lower. The phase noise is dependent on
the input source and measurement equipment.
ICS853S057AGI REVISION A MAY 16, 2012
5
©2012 Integrated Device Technology, Inc.

5 Page





ICS853S057I arduino
ICS853S057I Data Sheet
4:1, DIFFERENTIAL-TO-3.3V, 2.5V LVPECL/ECL CLOCK DATA MULTIPLEXER
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS53S057I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS53S057I is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
• Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 25mA = 86.625mW
• Power (outputs)MAX = 31.1mW/Loaded Output pair
Total Power_MAX (3.3V, with all outputs switching) = 86.625mW + 31.1mW = 117.725mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The
maximum recommended junction temperature for HiPerClockS devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 87.2°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.118W * 87.2°C/W = 95.3°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 6. Thermal Resistance θJA for 20 Lead TSSOP, Forced Convection
θJA by Velocity
Meters per Second
0
Multi-Layer PCB, JEDEC Standard Test Boards
87.2°C/W
1
82.9°C/W
2.5
80.7°C/W
ICS853S057AGI REVISION A MAY 16, 2012
11
©2012 Integrated Device Technology, Inc.

11 Page







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