|
|
PDF ICS853S01I Data sheet ( Hoja de datos )
| Número de pieza | ICS853S01I | |
| Descripción | 2:1 Differential-to-LVPECL Multiplexer | |
| Fabricantes | IDT | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de ICS853S01I (archivo pdf) en la parte inferior de esta página. Total 23 Páginas | ||
|
No Preview Available !
2:1 Differential-to-LVPECL Multiplexer
ICS853S01I
DATA SHEET
General Description
The ICS853S01I is a high performance 2:1 Differential-to-LVPECL
Multiplexer. The ICS853S01I can also perform differential translation
because the differential inputs accept LVPECL, LVDS and CML
levels. The ICS853S01I is packaged in a small 3mm x 3mm 16
VFQFN package, making it ideal for use on space constrained
boards.
Features
• One LVPECL output pair
• Two selectable differential LVPECL clock inputs
• PCLKx, nPCLKx pairs can accept the following
differential input levels: LVPECL, LVDS, CML
• Translates LVCMOS/LVTTL input signals to LVPECL levels by
using a resistor bias network on nPCLKx, nPCLKx
• Part-to-part skew: 150ps (maximum)
• Propagation delay: 490ps (maximum)
• Full 3.3V or 2.5V operating supply
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) packages
Block Diagram
PCLK0 Pulldown
nPCLK0 Pullup/Pulldown
PCLK1 Pulldown
nPCLK1 Pullup/Pulldown
0
1
CLK_SEL Pulldown
VBB
Q
nQ
Pin Assignments
16 15 14 13
PCLK0 1
12 VEE
nPCLK0 2
11 Q
PCLK1 3
10 nQ
nPCLK1 4
9 VEE
5 6 78
ICS853S01I
16-Lead VFQFN
3mm x 3mm x 0.925mm package body
K Package
Top View
PCLK0
nPCLK0
PCLK1
nPCLK1
VBB
CLK_SEL
nc
VCC
1
2
3
4
5
6
7
8
16 nc
15 VEE
14 VEE
13 VCC
12 VEE
11 Q
10 nQ
9 VEE
ICS853S01I
16-Lead TSSOP
4.4mm x 5.0mm x 0.925mm package body
G Package
Top View
ICS853S01AGI REVISION A OCTOBER 29, 2012
1
©2012 Integrated Device Technology, Inc.
1 page  
ICS853S01I Data Sheet
2:1 DIFFERENTIAL-TO-LVPECL MULTIPLEXER
AC Electrical Characteristics
Table 5A. AC Characteristics, VCC = 3.3V±5%; VEE = 0V, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
fOUT
tPD
tsk(i)
Output Frequency
Propagation Delay; NOTE 1
Input Skew
240
tsk(pp)
Part-to-Part Skew; NOTE 2, 3
tjit
Buffer Additive Phase Jitter, RMS,
refer to Additive Phase Jitter
section; NOTE 4
622MHz, Integration Range:
12kHz - 20MHz
tR / tF
MUXISOL
Output Rise/ Fall Time
MUX Isolation; NOTE 5
20% to 80%
ƒOUT 622MHz
100
Typical
0.024
81
Maximum
2.5
490
40
150
Units
GHz
ps
ps
ps
ps
240 ps
dB
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE: All parameters measured at ƒ 1.0GHz unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency and
with equal load conditions at the same temperature. Using the same type of inputs on each device, the outputs are measured at the differential
cross points.
NOTE 4: Driving only one input clock.
NOTE 5: Q, nQ output measured differentially. See Parameter Measurement Information for MUX Isolation diagram
Table 5B. AC Characteristics, VCC = 2.5V±5%; VEE = 0V, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
fOUT
tPD
tsk(i)
Output Frequency
Propagation Delay; NOTE 1
Input Skew
240
tsk(pp)
Part-to-Part Skew; NOTE 2, 3
tjit
Buffer Additive Phase Jitter, RMS,
refer to Additive Phase Jitter
section; NOTE 4
622MHz, Integration Range:
12kHz - 20MHz
tR / tF
MUXISOL
Output Rise/ Fall Time
MUX Isolation; NOTE 5
20% to 80%
ƒOUT 622MHz
100
Typical
0.024
81
Maximum
2.5
490
40
150
Units
GHz
ps
ps
ps
ps
240 ps
dB
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE: All parameters measured at ƒ 1.0GHz unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency and
with equal load conditions at the same temperature. Using the same type of inputs on each device, the outputs are measured at the differential
cross points.
NOTE 4: Driving only one input clock.
NOTE 5: Q, nQ output measured differentially. See Parameter Measurement Information for MUX Isolation diagram
ICS853S01AGI REVISION A OCTOBER 29, 2012
5
©2012 Integrated Device Technology, Inc.
5 Page 
ICS853S01I Data Sheet
2:1 DIFFERENTIAL-TO-LVPECL MULTIPLEXER
LVPECL Clock Input Interface (2.5V)
The PCLK /nPCLK accepts LVPECL, LVDS and other differential
signals. The differential signal must meet the VPP and VCMR input
requirements. Figures 3A to 3C show interface examples for the
PCLK/nPCLK input driven by the most common driver types. The
input interfaces suggested here are examples only. If the driver is
from another vendor, use their termination recommendation. Please
consult with the vendor of the driver component to confirm the driver
termination requirements.
2.5V
LVDS
Zo = 50Ω
Zo = 50Ω
2.5V
R1
100Ω
PCLK
nPCLK
LVPECL
Input
2. 5V
Zo = 50Ω
Zo = 50Ω
2.5V LVPECL Driv er
R6 R7
100Ω-180Ω 100Ω-180Ω
2.5V
R1
C1 100Ω
C2
R3
100Ω
PCLK
nPCLK
R2
100Ω
R4
100Ω
Figure 3A. PCLK/nPCLK Input Driven by a 2.5V LVDS
Driver
Figure 3B. PCLK/nPCLK Input Driven by a 3.3V LVPECL
Driver with AC Couple
2.5V
LVDS
Zo = 50Ω
Zo = 50Ω
2.5V
R1
100Ω
PCLK
nPCLK
LVPECL
Input
Figure 3C. PCLK/nPCLK Input Driven by a 2.5V LVPECL
Driver
ICS853S01AGI REVISION A OCTOBER 29, 2012
11
©2012 Integrated Device Technology, Inc.
11 Page | ||
| Páginas | Total 23 Páginas | |
| PDF Descargar | [ Datasheet ICS853S01I.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| ICS853S011BI | LVPECL/ECL Fanout Buffer | IDT |
| ICS853S011CI | LVPECL/ECL Fanout Buffer | IDT |
| ICS853S012I | LVPECL Clock/Data Multiplexer | IDT |
| ICS853S013I | LVPECL/ECL Fanout Buffer | IDT |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |