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PDF ICS853S011CI Data sheet ( Hoja de datos )
| Número de pieza | ICS853S011CI | |
| Descripción | LVPECL/ECL Fanout Buffer | |
| Fabricantes | IDT | |
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Low Skew, 1-to-2, Differential-to-2.5V, 3.3V ICS853S011CI
LVPECL/ECL Fanout Buffer
DATA SHEET
General Description
The ICS853S011CI is a low skew, high performance 1-to-2
Differential-to-2.5V/3.3V LVPECL/ECL Fanout Buffer. The
ICS853S011CI is characterized to operate from either a 2.5V or a
3.3V power supply. Guaranteed output and part-to-part skew
characteristics make the ICS853S011CI ideal for those clock
distribution applications demanding well defined performance and
repeatability.
Features
• Two differential 2.5V, 3.3V LVPECL/ECL outputs
• One differential PCLK, nPCLK input pair
• PCLK, nPCLK pairs can accept the following
differential input levels: LVPECL, LVDS, CML, SSTL
• Maximum output frequency: >2.5GHz
• Translates any single-ended input signal to 3.3V LVPECL levels
with resistor bias on nPCLK input
• Output skew: 20ps (maximum)
• Part-to-part skew: 150ps (maximum)
• Propagation delay: 330ps (maximum)
• LVPECL mode operating voltage supply range:
VCC = 2.375V to 3.8V, VEE = 0V
• ECL mode operating voltage supply range:
VCC = 0V, VEE = -3.8V to -2.375V
• -40°C to 85°C ambient operating temperature
• Lead-free (RoHS 6) packaging
Block Diagram
PCLK Pulldown
nPCLK Pullup/Pulldown
Q0
nQ0
Q1
nQ1
ICS853S011CGI REVISION A JULY 16, 2013
Pin Assignment
Q0 1
nQ0 2
Q1 3
nQ1 4
8 VCC
7 PCLK
6 nPCLK
5 VEE
ICS853S011CI
8-Lead SOIC, 150MIL
3.90mm x 4.90mm x 1.37mm package body
M Package
Top View
8-Lead TSSOP, 118MIL
3.0mm x 3.0mm x 0.97mm package body
G Package
Top View
1 ©2013 Integrated Device Technology, Inc.
1 page  
ICS853S011CI Data Sheet
LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
AC Electrical Characteristics
Table 4. AC Characteristics, VCC = -3.8V to -2.375V or , VCC = 2.375V to 3.8V; VEE = 0V,
TA = -40°C to 85°C
-40°C
25°C
Symbol Parameter
Min Typ Max Min Typ Max
fMAX
tPD
tsk(o)
Output Frequency
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
170
>2.5
320 180
20
>2.5
330
20
tsk(pp) Part-to-Part Skew; NOTE 3, 4
150 150
Buffer Additive Phase Jitter,
tjit RMS; refer to Additive Phase
Jitter Section
0.035
0.035
tR / tF
Output
Rise/Fall Time
20% to 80%
50
200 50
200
odc Output Duty Cycle
48 52 48 52
85°C
Min Typ Max
>2.5
190 345
20
150
0.035
50 200
48 52
Units
GHz
ps
ps
ps
ps
ps
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE: All parameters are measured at f 1.4GHz, unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential
cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using
the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
ICS853S011CGI REVISION A JULY 16, 2013
5
©2013 Integrated Device Technology, Inc.
5 Page 
ICS853S011CI Data Sheet
LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
The differential outputs are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50
transmission lines. Matched impedance techniques should be used
to maximize operating frequency and minimize signal distortion.
Figures 3A and 3B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts may
exist and it would be recommended that the board designers
simulate to guarantee compatibility across all printed circuit and clock
component process variations.
3.3V
LVPECL
3.3V
R3 R4
125
125
3.3V
Zo = 50
+
Zo = 50
R1
84
_
R2
84
Input
Figure 3A. 3.3V LVPECL Output Termination
Figure 3B. 3.3V LVPECL Output Termination
ICS853S011CGI REVISION A JULY 16, 2013
11
©2013 Integrated Device Technology, Inc.
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet ICS853S011CI.PDF ] | |
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