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PDF ICS853S024 Data sheet ( Hoja de datos )
| Número de pieza | ICS853S024 | |
| Descripción | LVPECL FANOUT BUFFER | |
| Fabricantes | IDT | |
| Logotipo |  |
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PRELIMINARY
LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-3.3V, 2.5V
LVPECL FANOUT BUFFER
ICS853S024
General Description
The ICS853S024 is a low skew, 1-to-24
ICS Differential-to-3.3V, 2.5V LVPECL Fanout Buffer and
HiPerClockS™ a member of theHiPerClockS™ family of High
Performance Clock Solutions from IDT. The CLK,
nCLK pair can accept most standard differential
input levels. The ICS853S024 is characterized to operate from
either a 3.3V or a 2.5V power supply. Guaranteed output skew
characteristics make the ICS853S024 ideal for those clock
distribution applications demanding well defined performance and
repeatability.
Features
• Twenty four LVPECL outputs.
• One differential clock input pair
• Differential input clock (CLK, nCLK) can accept the following
signaling levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
• Maximum output frequency: >1.5GHz
• Translates any single ended input signal to 3.3V/ 2.5V LVPECL
levels with resistor bias on nCLK input
• Output skew: 25ps (typical)
• tR / tF: 180ps (typical)
• Additive phase jitter, RMS: 0.111ps (typical) @ 312.5MHz
• Full 3.3V or 2.5V supply voltage
• 0°C to 70°C ambient operating temperature
• Available in lead-free (RoHS 6) packages.
.
Block Diagram
CLK Pulldown
nCLK Pullup
24
Q0:Q23
24 nQ0:nQ23
Pin Assignment
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
VCC 1
48 nCLK
VEE 2
47 CLK
Q0 3
nQ0 4
ICS853S024
46 nQ17
45 Q17
Q1
nQ1
Q2
nQ2
5
6
7
8
64-Lead TQFP, EPad
10mm x 10mm x 1mm
package body
44 nQ16
43 Q16
42 nQ15
41 Q15
Q3
nQ3
Q4
9
10
11
Y Package
Top View
40 nQ14
39 Q14
38 nQ13
nQ4 12
37 Q13
Q5 13
36 nQ12
nQ5 14
35 Q12
VEE 15
34 VCC
VCC 16
33 VCC
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification.
Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
LOW SKEW LVPECL FANOUT BUFFER 1 ICS853S024AY REV. A APRIL 30, 2008
1 page  
ICS853S024
LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-3.3V, 2.5V LVPECL FANOUT BUFFER
Parameter Measurement Information
2V 2V
PRELIMINARY
VCC
SCOPE
Qx
LVPECL
VEE
nQx
-1.3V ± 0.165V
3.3V LVPECL Output Load AC Test Circuit
VCC
SCOPE
Qx
LVPECL
VEE
nQx
-0.5V ± 0.125V
2.5V LVPECL Output Load AC Test Circuit
VCC
nCLK
CLK
V
PP
VEE
Cross Points
Differential Input Level
V
CMR
nQx
Qx
nQy
Qy
t sk(o)
Output Skew
Part 1
nQx
Qx
nQy Par t 2
Qy
t sk(pp)
Part-to-Part Skew
nCLK
CLK
nQ0:nQ21
Q0:Q21
tPD
Propagation Delay
LOW SKEW LVPECL FANOUT BUFFER 5 ICS853S024AY REV. A APRIL 30, 2008
5 Page 
ICS853S024
LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-3.3V, 2.5V LVPECL FANOUT BUFFER
PRELIMINARY
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS853S024.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS853S024 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
• Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 200mA = 693mW
• Power (outputs)MAX = 30mW/Loaded Output pair
If all outputs are loaded, the total power is 24 * 30mW = 720mW
Total Power_MAX (3.465V, with all outputs switching) = 693W + 720mW = 1.413W
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device.
The maximum recommended junction temperature for HiPerClockS devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming 0 air flow
and a multi-layer board, the appropriate value is 32.5°C/W per Table 5 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 1.413 W * 32.5°C/W = 115.9°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type
of board (single layer or multi-layer).
Table 5. Thermal Resistance θJA for 64 Lead TQFP, EPad, Forced Convection
θJA by Velocity
Meters per Second
0
1
Multi-Layer PCB, JEDEC Standard Test Boards
32.5°C/W
26.6°C/W
2.5
25.1°C/W
LOW SKEW LVPECL FANOUT BUFFER
11 ICS853S024AY REV. A APRIL 30, 2008
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet ICS853S024.PDF ] | |
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