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PDF 8413S12I-100 Data sheet ( Hoja de datos )

Número de pieza 8413S12I-100
Descripción Clock Generator
Fabricantes IDT 
Logotipo IDT Logotipo



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No Preview Available ! 8413S12I-100 Hoja de datos, Descripción, Manual

Clock Generator for Cavium
Processors
8413S12I-100
Data Sheet
General Description
Features
The 8413S12I-100 is a PLL-based clock generator specifically
designed for Cavium Networks Octeon II processors. This high
performance device is optimized to generate the processor core
reference clock, the PCI-Express reference clocks and the clocks for
both the Gigabit Ethernet MAC and PHY. The clock generator offers
ultra low-jitter, low-skew clock outputs, and edge rates that easily
meet the input requirements for the CN63XX and CN68XX series of
processors. The output frequencies are generated from a 25MHz
external input source or an external 25MHz parallel resonant crystal.
The industrial temperature range of the 8413S12I-100 supports
telecommunication, networking, and storage requirements.
Applications
Systems using Cavium Processors
CPE Gateway Design
Home Media Servers
802.11n AP or Gateway
Soho Secure Gateway
Soho SME Gateway
Wireless Soho and SME VPN Solutions
Wired and Wireless Network Security
Web Servers and Exchange Servers
Ten 100MHz clocks for PCI Express, HCSL interface levels
One single-ended QG LVCMOS/LVTTL clock output at 125MHz
One single-ended QF LVCMOS/LVTTL clock output at 50MHz,
15output impedance
Two single-ended QREFx LVCMOS/LVTTL outputs at 25MHz,
15output impedance
Selectable external crystal or differential (single-ended) input
source
Crystal oscillator interface designed for 25MHz, parallel resonant
crystal
Differential CLK, nCLK input pair that can accept: LVPECL, LVDS,
LVHSTL, HCSL input levels
Internal resistor bias on nCLK pin allows the user to drive CLK
input with external single-ended (LVCMOS/ LVTTL) input levels
Supply Modes, (125MHz QG output and 25MHz QREFx outputs):
Core / Output
3.3V / 3.3V
3.3V / 2.5V
Supply Modes, (HCSL outputs, and 50MHz QF output):
Core / Output
3.3V / 3.3V
-40°C to 85°C ambient operating temperature
Available in Lead-free (RoHS 6) package
Pin Assignment
GND
nc
nc
nc
nc
nc
nc
nc
nc
nc
VDDA
nc
nc
XTAL_IN
XTAL_OUT
nc
REF_SEL
GND
72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55
1 54
2 53
3 52
4 51
5 50
6 8XXXXXX
7
49
48
8 47
9
10
8413S12I-100
46
45
11 44
12 43
13 42
14 41
15 40
16 39
17 38
18 37
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
nc
VDD
IREF
OE_D
nQD1
QD1
nQD0
QD0
VDDO_D
VDDO_C
nQC1
QC1
nQC0
QC0
OE_C
VDD
GND
nc
©2016 Integrated Device Technology, Inc.
72-pin, 10mm x 10mm LQFP Package
1 October 4, 2016

1 page




8413S12I-100 pdf
Function Tables
Table 3A. PLL_SEL Control Input Function Table
Input
PLL_SEL
Operation
0 PLL Bypass
1 (default)
PLL Mode
Table 3B. REF_SEL Control Input Function Table
Input
REF_SEL
Clock Source
0 CLK, nCLK
1 (default)
XTAL_IN,
XTAL_OUT
Table 3C. OE_[A:E] Control Input Function Table
Input
Outputs
OE_[A:E]
Q[Ax:Ex], nQ[Ax:Ex]
0 High-Impedance
1 (default)
Enabled
Table 3D. OE_G Control Input Function Table
Input
Outputs
OE_G
QG
0 High-Impedance
1 (default)
Enabled
Table 3E. OE_REF Control Input Function Table
Input
Output
OE_REF
QREF[1:0]
0 High-Impedance
1 (default)
Enabled
8413S12I-100 Data Sheet
©2016 Integrated Device Technology, Inc.
5
October 4, 2016

5 Page





8413S12I-100 arduino
Typical Phase Noise at 100MHz
8413S12I-100 Data Sheet
100MHz
RMS Phase Jitter (Random)
12kHz to 20MHz = 0.68ps (typical)
Offset Frequency (Hz)
©2016 Integrated Device Technology, Inc.
11
October 4, 2016

11 Page







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