PDF CD40108BMS Data sheet ( Hoja de datos )

Número de pieza	CD40108BMS
Descripción	CMOS 4 x 4 Multiport Register
Fabricantes	Intersil Corporation
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CD40108BMS December 1992 CMOS 4 x 4 Multiport Register Features Description • High Voltage Type (20V Rating) • Four 4-Bit Registers • One Input and Two Output Buses • Unlimited Expansion in Bit and Word Directions • Data Lines have latched Inputs • 3-State Outputs • Separate Control of Each Bus, Allowing Simultaneous Independent Reading of Any of Four Registers on Bus A and Bus B and Independent Writing Into Any of the Four Registers • CD40108BMS is Pin-Compatible with Industry Type MC14580 • Standardized Symmetrical Output Characteristics • 100% Tested for Quiescent Current at 20V • Maximum Input Current of 1µA at 18V Over Full Pack- age Temperature Range; 100nA at 18V and +25oC • Noise Margin (Over Full Package/Temperature Range) - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V • 5V, 10V and 15V Parametric Ratings • Meets All Requirements of JEDEC Tentative Standard No. 13B, “Standard Speciﬁcations for Description of ‘B’ Series CMOS Devices” The CD40108BMS is a 4 x 4 multiport register containing four 4-bit registers, write address decoder, two separate read address decoders, and two 3-state output buses. When the ENABLE input is low, the corresponding output bus is switched, independently of the clock, to a high-imped- ance state. The high-impedance third state provides the out- puts with the capability of being connected to the bus lines in a bus-organized system without the need for interface or pull-up components. When the WRITE ENABLE input is high, all data input lines are latched on the positive transition of the CLOCK and the data is entered into the word selected by the write address lines. When WRITE ENABLE is low, the CLOCK is inhibited and no new data is entered. In either case, the contents of any word may be accessed via the read address lines inde- pendent of the state of the CLOCK input. The CD40108BMS is supplied in these 24-lead outline pack- ages: Braze Seal DIP Ceramic Flatpack H4V H4P Applications • Scratch-Pad Memories • Arithmetic Units • Data Storage Pinout CD40108BMS TOP VIEW Q3 B 1 Q2 B 2 3-STATE A 3 Q0 A 4 Q1 A 5 Q2 A 6 Q3 A 7 WRITE 0 8 WRITE 1 9 READ 1B 10 READ 0B 11 VSS 12 24 VDD 23 Q1 B 22 Q0 B 21 3-STATE B 20 D0 19 D1 18 D2 17 D3 16 CLOCK 15 WRITE ENABLE 14 READ 1A 13 READ 0A Functional Diagram WRITE ENABLE 15 DATA INPUTS D0 20 D1 19 D2 18 D3 17 3-STATE A 3 4 Q0 5 Q1 6 Q2 7 Q3 WORD A OUTPUT WRITE 0 WRITE 1 8 9 READ 1A 14 READ 0A 13 VDD = 24 VSS = 12 READ 1B 10 READ 0B 11 16 CLOCK 22 Q0 23 Q1 2 Q2 1 Q3 WORD B OUTPUT 21 3-STATE B CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 \| Copyright © Intersil Corporation 1999 7-25 File Number 3356 1 page Speciﬁcations CD40108BMS TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER Minimum Clock Pulse Width Clock or Write Enable Minimum Clock Pulse Width Write Address Input Capacitance SYMBOL CONDITIONS TW VDD = 5V VDD = 10V VDD = 15V TW VDD = 5V VDD = 10V VDD = 15V CIN Any Input NOTES 3 3 3 3 3 3 1, 2 TEMPERATURE +25oC +25oC +25oC +25oC +25oC +25oC +25oC MIN - - - - - - - MAX 350 130 90 300 150 90 7.5 UNITS ns ns ns ns ns ns pF NOTES: 1. All voltages referenced to device GND. 2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics. 3. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 4. CL = 50pF, RL = 1K, Input TR, TF < 20ns. 5. If more than one unit is cascaded, TRCL should be made less than or equal to the sumof the transition time and the fixed propagation delay of the output of the driving stage for the estimated capacitive load. TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current N Threshold Voltage N Threshold Voltage Delta P Threshold Voltage P Threshold Voltage Delta Functional Propagation Delay Time SYMBOL CONDITIONS IDD VDD = 20V, VIN = VDD or GND VNTH VDD = 10V, ISS = -10µA ∆VTN VDD = 10V, ISS = -10µA VTP ∆VTP VSS = 0V, IDD = 10µA VSS = 0V, IDD = 10µA F TPHL TPLH VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND VDD = 5V NOTES: 1. All voltages referenced to device GND. 2. CL = 50pF, RL = 200K, Input TR, TF < 20ns. NOTES 1, 4 1, 4 1, 4 TEMPERATURE +25oC +25oC +25oC MIN - -2.8 - 1, 4 +25oC 0.2 1, 4 +25oC - 1 1, 2, 3, 4 +25oC +25oC VOH > VDD/2 - 3. See Table 2 for +25oC limit. 4. Read and Record MAX 25 -0.2 ±1 2.8 ±1 VOL < VDD/2 1.35 x +25oC Limit UNITS µA V V V V V ns TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25oC PARAMETER SYMBOL DELTA LIMIT Supply Current - MSI-2 Output Current (Sink) Output Current (Source) IDD IOL5 IOH5A ± 1.0µA ± 20% x Pre-Test Reading ± 20% x Pre-Test Reading CONFORMANCE GROUP Initial Test (Pre Burn-In) TABLE 6. APPLICABLE SUBGROUPS MIL-STD-883 METHOD GROUP A SUBGROUPS 100% 5004 1, 7, 9 READ AND RECORD IDD, IOL5, IOH5A 7-29 5 Page CD40108BMS Q 1kΩ TO ANY OUTPUT 50pF 1 2 3 4 5 6 7 8 9 10 11 12 24 PULSE GEN. 2 23 P.G. 1 CL 22 21 20 19 D 18 17 16 PULSE GEN. 1 15 14 P.G. 2 ENABLE INPUT 50% tPLZ Q OUTPUTS tPHZ ENABLE 10% 90% VDD 50% VSS tPZL 90% VDD VOL VOH 10% VSS tPZH 13 TEST VOLTAGE CHAR AT D AT Q tPHZ tPZH VDD VDD VSS VSS tPLZ VSS VDD tPZL VSS VDD FIGURE 12. OUTPUT-ENABLE-DELAY-TIMES TEST CIRCUIT AND WAVEFORMS Chip Dimensions and Pad Layout Dimensions in parenthesis are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch). METALLIZATION: Thickness: 11kÅ − 14kÅ, AL. PASSIVATION: 10.4kÅ - 15.6kÅ, Silane BOND PADS: 0.004 inches X 0.004 inches MIN DIE THICKNESS: 0.0198 inches - 0.0218 inches 7-35 11 Page

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