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PDF KSZ8463RL Data sheet ( Hoja de datos )

Número de pieza KSZ8463RL
Descripción ETHERSYNCH product line consists of IEEE 1588v2 enabled Ethernet switches
Fabricantes Micrel Semiconductor 
Logotipo Micrel Semiconductor Logotipo



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KSZ8463ML/RL/FML/FRL
IEEE 1588 Precision Time Protocol-
Enabled, Three-Port, 10/100-Managed
Switch with MII or RMII
Revision 1.0
General Description
The KSZ8463 ETHERSYNCH™ product line consists of
IEEE 1588v2 enabled Ethernet switches, providing
integrated communications and synchronization for a
range of Industrial Ethernet applications.
The KSZ8463 ETHERSYNCH product line enables
distributed, daisy-chained topologies preferred for
Industrial Ethernet networks. Conventional centralized
(i.e., star-wired) topologies are also supported for dual-
homed, fault-tolerant arrangements.
A flexible set of standard MAC interfaces is provided to
interface to external host processors with embedded
Ethernet MACs:
KSZ8463ML: Media Independent Interface (MII)
KSZ8463RL: Reduced Media Independent Interface
(RMII)
KSZ8463FML: MII, supports 100BASE-FX fiber in
addition to 10/100BASE-TX copper
KSZ8463FRL: RMII, supports 100BASE-FX fiber in
addition to 10/100BASE-TX copper
The KSZ8463 devices incorporate the IEEE 1588v2
protocol. Sub-microsecond synchronization is available via
the use of hardware-based time-stamping and transparent
clocks making it the ideal solution for time synchronized
Layer 2 communication in critical industrial applications.
Extensive general purpose I/O (GPIO) capabilities are
available to use with the IEEE 1588v2 PTP to efficiently
and accurately interface to locally connected devices.
Complementing the industry’s most-integrated IEEE
1588v2 device is a precision timing protocol (PTP) v2
software stack that has been pre-qualified with the
KSZ84xx product family. The PTP stack has been
optimized around the KSZ84xx chip architecture, and is
available in source code format along with Micrel’s chip
driver.
ETHERSYNCH™
The KSZ8463 product line is built upon Micrel’s industry-
leading Ethernet technology, with features designed to
offload host processing and streamline your overall design.
Wire-speed Ethernet switching fabric with extensive
filtering
Two integrated 10/100BASE-TX PHY transceivers,
featuring the industry’s lowest power consumption
Full-featured quality-of-service (QoS) support
Flexible management options that support common
standard interfaces
The wire-speed, store-and-forward switching fabric
provides a full complement of QoS and congestion control
features optimized for real-time Ethernet.
A robust assortment of power-management features
including energy-efficient Ethernet (EEE) have been
designed in to satisfy energy efficient environments.
Datasheets and support documentation are available on
Micrel’s web site at: www.micrel.com.
Functional Diagram
ETHERSYNCH is a trademark of Micrel, Inc.
LinkMD is a registered trademark of Micrel, Inc.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
June 11, 2014
Revision 1.0

1 page




KSZ8463RL pdf
Micrel, Inc.
KSZ8463ML/RL/FML/FRL
Ordering Information
Part Number
KSZ8463MLI
KSZ8463FMLI
KSZ8463RLI
KSZ8463FRLI
KSZ8463MLI-EVAL
Temperature Range
–40oC to +85oC
Package
64-Pin LQFP
Lead Finish Description
Pb-Free Industrial Temperature Device with MII Interface
–40oC to +85oC
–40oC to +85oC
64-Pin LQFP
64-Pin LQFP
Pb-Free
Pb-Free
Industrial Temperature Device with MII Interface
and Fiber (100BASE-FX) support
Industrial Temperature Device with RMII Interface
–40oC to +85oC
64-Pin LQFP
Pb-Free
Industrial Temperature Device with RMII Interface
and Fiber (100BASE-FX) support
Evaluation Board with KSZ8463MLI. Also supports KSZ8463FMLI, KSZ8463RLI and KSZ8463FRLI.
Revision History
Revision
1.0
Date
6/11/14
Summary of Changes
Initial release of product S. Thompson
June 11, 2014
5
Revision 1.0

5 Page





KSZ8463RL arduino
Micrel, Inc.
KSZ8463ML/RL/FML/FRL
Internal I/O Register Space Mapping for Trigger Output Units (12 Units, 0x200 – 0x3FF) ................................................ 195
Trigger Error Register (0x200 – 0x201): TRIG_ERR ...................................................................................................... 195
Trigger Active Register (0x202 – 0x203): TRIG_ACTIVE ............................................................................................... 195
Trigger Done Register (0x204 – 0x205): TRIG_DONE ................................................................................................... 195
Trigger Enable Register (0x206 – 0x207): TRIG_EN...................................................................................................... 196
Trigger Software Reset Register (0x208 – 0x209): TRIG_SW_RST .............................................................................. 196
Trigger Output Unit 12 Output PPS Pulse-Width Register (0x20A – 0x20B): TRIG12_PPS_WIDTH ............................ 196
0x20C – 0x21F: Reserved............................................................................................................................................... 196
Trigger Output Unit 1 Target Time in Nanoseconds Low-Word Register (0x220 – 0x221): TRIG1_TGT_NSL ............. 197
Trigger Output Unit 1 Target Time in Nanoseconds High-Word Register (0x222 – 0x223): TRIG1_TGT_NSH ............ 197
Trigger Output Unit 1 Target Time in Seconds Low-Word Register (0x224 – 0x225): TRIG1_TGT_SL ........................ 197
Trigger Output Unit 1 Target Time in Seconds High-Word Register (0x226 – 0x227): TRIG1_TGT_SH....................... 197
Trigger Output Unit 1 Configuration and Control Register 1 (0x228 – 0x229): TRIG1_CFG_1...................................... 197
Trigger Output Unit 1 Configuration and Control Register 2 (0x22A – 0x22B): TRIG1_CFG_2..................................... 199
Trigger Output Unit 1 Configuration and Control Register 3 (0x22C – 0x22D): TRIG1_CFG_3 .................................... 199
Trigger Output Unit 1 Configuration and Control Register 4 (0x22E – 0x22F): TRIG1_CFG_4 ..................................... 199
Trigger Output Unit 1 Configuration and Control Register 5 (0x230 – 0x231): TRIG1_CFG_5...................................... 199
Trigger Output Unit 1 Configuration and Control Register 6 (0x232 – 0x233): TRIG1_CFG_6...................................... 200
Trigger Output Unit 1 Configuration and Control Register 7 (0x234 – 0x235): TRIG1_CFG_7...................................... 200
Trigger Output Unit 1 Configuration and Control Register 8 (0x236 – 0x237): TRIG1_CFG_8...................................... 200
0x238 – 0x23F: Reserved ............................................................................................................................................... 200
Trigger Output Unit 2 Target Time and Output Configuration/Control Registers (0x240 – 0x257)................................. 200
Trigger Output Unit 2 Configuration and Control Register 1 (0x248 – 0x249): TRIG2_CFG_1...................................... 201
0x258 – 0x25F: Reserved ............................................................................................................................................... 201
Trigger Output Unit 3 Target Time and Output Configuration/Control Registers (0x260 – 0x277)................................. 201
0x278 – 0x27F: Reserved ............................................................................................................................................... 201
Trigger Output Unit 4 Target Time and Output Configuration/Control Registers (0x280 – 0x297)................................. 201
0x298 – 0x29F: Reserved ............................................................................................................................................... 201
Trigger Output Unit 5 Target Time and Output Configuration/Control Registers (0x2A0 – 0x2B7) ................................ 201
0x2B8 – 0x2BF: Reserved............................................................................................................................................... 201
Trigger Output Unit 6 Target Time and Output Configuration/Control Registers (0x2C0 – 0x2D7)................................ 201
0x2D8 – 0x2DF: Reserved .............................................................................................................................................. 201
Trigger Output Unit 7 Target Time and Output Configuration/Control Registers (0x2E0 – 0x2F7) ................................ 202
0x2F8 – 0x2FF: Reserved ............................................................................................................................................... 202
Trigger Output Unit 8 Target Time and Output Configuration/Control Registers (0x300 – 0x317)................................. 202
0x318 – 0x31F: Reserved ............................................................................................................................................... 202
Trigger Output Unit 9 Target Time and Output Configuration/Control Registers (0x320 – 0x337)................................. 202
0x338 – 0x33F: Reserved ............................................................................................................................................... 202
Trigger Output Unit 10 Target Time and Output Configuration/Control Registers (0x340 – 0x357) ............................... 202
0x358 – 0x35F: Reserved ............................................................................................................................................... 202
Trigger Output Unit 11 Target Time and Output Configuration/Control Registers (0x360 – 0x377) ............................... 202
0x378 – 0x37F: Reserved ............................................................................................................................................... 202
Trigger Output Unit 12 Target Time and Output Configuration/Control Registers (0x380 – 0x397) ............................... 202
0x398 – 0x3FF: Reserved ............................................................................................................................................... 202
June 11, 2014
11
Revision 1.0

11 Page







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