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PDF KTS6029 Data sheet ( Hoja de datos )
| Número de pieza | KTS6029 | |
| Descripción | 2 Band TV Tuner | |
| Fabricantes | SIEMENS | |
| Logotipo |  |
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Components
for Entertainment Electronics
2 Band TV Tuner
KTS6027, KTS6029
Mixer-Oscillator-PLL
with unbalanced IF-Amplifier
Preliminary Data Sheet 06.99
1 page  
2 Band TV Tuner
Mixer-Oscillator-PLL
with unbalanced IF-Amplifier
KTS6027, KTS6029
Preliminary Data Sheet
1 Features
General
• Suitable for TV tuners
• Full ESD protection
Mixer/Oscillator
• High impedance mixer input for VHF
• Low impedance mixer input for UHF
• 4 pin oscillator for VHF
• 4 pin oscillator for UHF
IF-Amplifier
• unbalanced SAW preamplifier
• Low output impedance
PLL
• PLL with short lock-in time;
no asynchronous divider stage
• High voltage VCO tuning output
• Fast I2C bus
• 4 NPN bandswitch buffers
• Internal VHF/UHF switch
• Lock-in flag
• Power-down reset
• Programmable reference divider ratio
(64, 80, 128)
• Programmable charge pump current
P-TSSOP-28-1
Package
BIPOLAR
2 Ordering Information
Type
KTS6027XS
KTS6027-K
KTS6027-S
KTS6029XS
KTS6029-K
KTS6029-S
Package
P-TSSOP-28-1
P-TSSOP-28-1
P-TSSOP-28-1
P-TSSOP-28-1
P-TSSOP-28-1
P-TSSOP-28-1
Ordering Code
Q67037-A1087
Q67037-A1088
Q67037-A1059
Q67037-A1089
Q67037-A1090
Q67037-A1091
Semiconductor Group
1
2.6.99
5 Page 
Preliminary Data Sheet
KTS6027, KTS6029
9.3 I2C-Bus Interface
Data is exchanged between the processor and the PLL via the I2C bus. The clock is generated by the proces-
sor (input SCL), while pin SDA functions as an input or output depending on the direction of the data (open
collector, external pull-up resistor). Both inputs have hysteresis and a low-pass characteristic, which enhance
the noise immunity of the I2C bus.
The data from the processor pass through an I2C bus controller. Depending on their function the data are sub-
sequently stored in registers. If the bus is free, both lines will be in the marking state (SDA, SCL are HIGH).
Each telegram begins with the start condition and ends with the stop condition. Start condition: SDA goes
LOW, while SCL remains HIGH. Stop condition: SDA goes HIGH while SCL remains HIGH. All further infor-
mation transfer takes place during SCL = LOW, and the data is forwarded to the control logic on the positive
clock edge.
The table ”Bit Allocation” (see 9.3.1 Bit Allocation Read / Write on page 8) should be referred to the following
description. All telegrams are transmitted byte-by-byte, followed by a ninth clock pulse, during which the con-
trol logic returns the SDA line to LOW (acknowledge condition). The first byte is comprised of seven address
bits. These are used by the processor to select the PLL from several peripheral components (chip select). The
LSB bit (R/W) determines whether data are written into (R/W = 0) or read from (R/W = 1) the PLL.
In the data portion of the telegram during a WRITE operation, the MSB bit of the first or third data byte deter-
mines whether a divider ratio or control information is to follow. In each case the second byte of the same data
type has to follow the first byte.
If the address byte indicates a READ operation, the PLL generates an acknowledge and then shifts out the
status byte onto the SDA line. If the processor generates an acknowledge, a further status byte is output; oth-
erwise the data line is released to allow the processor to generate a stop condition. The status word consists
of two bits from the TTL input ports, three bits from the A/D converter, the lock flag and the power-on flag.
Four different chip addresses can be set by appropriate cDC level atf pin CAS (see 9.3.4 Address selection on
page 9).
When the supply voltage is applied, a power-on reset circuit prevents the PLL from setting the SDA line to
LOW, which would block the bus. The power-on reset flag POR is set at power-on and if VVCC falls below
3.2 V. It will be reset at the end of a READ operation.
Semiconductor Group
7
2.6.99
11 Page | ||
| Páginas | Total 25 Páginas | |
| PDF Descargar | [ Datasheet KTS6029.PDF ] | |
Hoja de datos destacado
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