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Número de pieza | CD4009UBMS | |
Descripción | CMOS Hex Buffers/Converter | |
Fabricantes | Intersil Corporation | |
Logotipo | ||
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No Preview Available ! Data Sheet
CD4009UBMS
November 1994
File Number 3293
CMOS Hex Buffers/Converter
CD4009UBMS Hex Buffer/Converter may be used as a
CMOS to TTL or DTL logic-level converter or a CMOS high-
sink-current driver.
The CD4049UB is the preferred hex buffer replacement for
the CD4009UBMS in all applications except multiplexers.
For applications not requiring high sink current or voltage
conversion, the CD4069UB Hex Inverter is recommended.
The CD4009UBMS is supplied in these 16 lead outline pack-
ages:
Braze Seal DIP H4S
Frit Seal DIP
H1E
Ceramic Flatpack H3X
Pinout
CD4009UBMS
TOP VIEW
VCC 1
G=A 2
A3
H=B 4
B5
I=C 6
C7
VSS 8
NC = NO CONNECTION
16 VDD
15 L = F
14 F
13 NC
12 K = E
11 E
10 J = D
9D
Features
• Inverting Type
• High-Voltage Type (20V Rating)
• 100% Tested for Quiescent Current at 20V
• Maximum Input Current of 1µA at 18V Over Full
Package-Temperature Range;
- 10nA at 18V and +25oC
• 5V, 10V and 15V Parametric Ratings
Applications
• CMOS To DTL/TTL Hex Converter
• CMOS Current “Sink” or “Source” Driver
• CMOS High-to-Low Logic-Level Converter
• Multiplexer - 1 to 6 or 6 to 1
Functional Diagram
3
A
2
G=A
5
B
4
H=B
NC
VCC
VSS
VDD
13
1
8
16
7
C
9
D
11
E
14
F
6
I=C
10
J=D
12
K=E
15
L=F
NC = NO CONNECTION
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
1 page CD4009UBMS
TABLE 6. APPLICABLE SUBGROUPS
CONFORMANCE GROUP
MIL-STD-883
METHOD
GROUP A SUBGROUPS
Initial Test (Pre Burn-In)
100% 5004
1, 7, 9
Interim Test 1 (Post Burn-In)
100% 5004
1, 7, 9
Interim Test 2 (Post Burn-In)
100% 5004
1, 7, 9
PDA (Note 1)
100% 5004
1, 7, 9, Deltas
Interim Test 3 (Post Burn-In)
100% 5004
1, 7, 9
PDA (Note 1)
100% 5004
1, 7, 9, Deltas
Final Test
100% 5004
2, 3, 8A, 8B, 10, 11
Group A
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11
Group B
Subgroup B-5
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
Subgroup B-6
Sample 5005
1, 7, 9
Group D
Sample 5005
1, 2, 3, 8A, 8B, 9
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.
READ AND RECORD
IDD, IOL5, IOH5A
IDD, IOL5, IOH5A
IDD, IOL5, IOH5A
IDD, IOL5, IOH5A
Subgroups 1, 2, 3, 9, 10, 11
Subgroups 1, 2 3
CONFORMANCE GROUPS
Group E Subgroup 2
TABLE 7. TOTAL DOSE IRRADIATION
MIL-STD-883
METHOD
TEST
PRE-IRRAD
POST-IRRAD
5005
1, 7, 9
Table 4
READ AND RECORD
PRE-IRRAD
POST-IRRAD
1, 9 Table 4
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
OSCILLATOR
FUNCTION
OPEN
GROUND
VDD
9V ± -0.5V
50kHz
25kHz
Static Burn-In 1 Note 1 2, 4, 6, 10, 12, 13, 15 3, 5, 7 - 9, 11, 14
1, 16
Static Burn-In 2 Note 1 2, 4, 6, 10, 12, 13, 15 8 1, 3, 5, 7, 9, 11, 14, 16
Dynamic Burn-In Note 1
13
8
1, 16
2, 4, 6, 10, 12, 15 3, 5, 7, 9, 11, 14
Irradiation Note 2
2, 4, 6, 10, 12, 13, 15
8
1, 3, 5, 7, 9, 11, 14, 16
NOTE:
1. Each pin except VDD and Pin 1 and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V
2. Each pin except VDD and Pin 1 and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures,
VDD = 10V ± 0.5V
Schematic Diagram
*
INPUT
VDD
GND
VDD
P
N
VCC
*ALL INPUTS ARE PROTECTED
BY CMOS PROTECTION
NETWORK
VDD
NP
OUTPUT
VCC
GND
N CONFIGURATION:
HEX COS/MOS TO DTL OR TTL
CONVERTER (INVERTING)
VSS
WIRING SCHEDULE:
CONNECT VCC TO DTL OR
TTL SUPPLY
CONNECT VDD TO COS/MOS
SUPPLY
VSS
5
5 Page |
Páginas | Total 8 Páginas | |
PDF Descargar | [ Datasheet CD4009UBMS.PDF ] |
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