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PDF MC14007UB Data sheet ( Hoja de datos )

Número de pieza MC14007UB
Descripción Dual Complementary Pair Plus Inverter
Fabricantes Motorola Semiconductors 
Logotipo Motorola Semiconductors Logotipo



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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Dual Complementary Pair
Plus Inverter
The MC14007UB multi–purpose device consists of three N–channel and
three P–channel enhancement mode devices packaged to provide access to
each device. These versatile parts are useful in inverter circuits, pulse–
shapers, linear amplifiers, high input impedance amplifiers, threshold
detectors, transmission gating, and functional gating.
Diode Protection on All Inputs
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range
Pin–for–Pin Replacement for CD4007A or CD4007UB
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎThis device has 2 outputs without ESD Protection. Anti–static
precautions must be taken.
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎMAXIMUM RATINGS* (Voltages Referenced to VSS)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSymbol
Parameter
Value
Unit
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVDD DC Supply Voltage
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVin, Vout Input or Output Voltage (DC or Transient)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎlin, lout Input or Output Current (DC or Transient),
per Pin
– 0.5 to + 18.0
– 0.5 to VDD + 0.5
± 10
V
V
mA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎPD Power Dissipation, per Package†
500 mW
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTstg Storage Temperature
– 65 to + 150
_C
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTL Lead Temperature (8–Second Soldering)
260 _C
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ*Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C
INPUT
A
B 12
1
C3
VDD 5
14
INPUT OUTPUT CONDITION
1 A = C, B = OPEN
0 A = B, C = OPEN
INPUT
6
Substrates of P–channel devices internally
connected to VDD; substrates of N–channel
devices internally connected to VSS.
13
8
7 VSS
A
9
B
2
4
C
11
10
Figure 1. Typical Application: 2–Input Analog Multiplexer
MC14007UB
L SUFFIX
CERAMIC
CASE 632
P SUFFIX
PLASTIC
CASE 646
D SUFFIX
SOIC
CASE 751A
ORDERING INFORMATION
MC14XXXUBCP
MC14XXXUBCL
MC14XXXUBD
Plastic
Ceramic
SOIC
TA = – 55° to 125°C for all packages.
PIN ASSIGNMENT
D–PB
S–PB
GATEB
S–NB
D–NB
GATEA
VSS
1 14
2 13
3 12
4 11
5 10
69
78
D = DRAIN
S = SOURCE
VDD
D–PA
OUTC
S–PC
GATEC
S–NC
D–NA
SCHEMATIC
14 13
21
11
6 12
78 3
4 5 10
VDD = PIN 14
VSS = PIN 7
9
REV 3
1/94
©MMOotoTrOolaR, IOncL. A199C5MOS LOGIC DATA
MC14007UB
31

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MC14007UB pdf
OUTLINE DIMENSIONS
L SUFFIX
CERAMIC DIP PACKAGE
CASE 632–08
ISSUE Y
–A–
14 9
–B–
17
CL
–T–
SEATING
PLANE
F
GN
D 14 PL
0.25 (0.010) M T A S
K
M
J 14 PL
0.25 (0.010) M T B S
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
INCHES
MILLIMETERS
DIM MIN MAX MIN MAX
A 0.750 0.785 19.05 19.94
B 0.245 0.280 6.23 7.11
C 0.155 0.200 3.94 5.08
D 0.015 0.020 0.39 0.50
F 0.055 0.065 1.40 1.65
G 0.100 BSC
2.54 BSC
J 0.008 0.015 0.21 0.38
K 0.125 0.170 3.18 4.31
L 0.300 BSC
7.62 BSC
M 0_ 15_ 0_ 15_
N 0.020 0.040 0.51 1.01
14
1
A
F
HG
8
B
7
P SUFFIX
PLASTIC DIP PACKAGE
CASE 646–06
ISSUE L
C
N
SEATING
PLANE
D
K
L
J
M
NOTES:
1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE
POSITION AT SEATING PLANE AT MAXIMUM
MATERIAL CONDITION.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
4. ROUNDED CORNERS OPTIONAL.
INCHES
MILLIMETERS
DIM MIN MAX MIN MAX
A 0.715 0.770 18.16 19.56
B 0.240 0.260 6.10 6.60
C 0.145 0.185 3.69 4.69
D 0.015 0.021 0.38 0.53
F 0.040 0.070 1.02 1.78
G 0.100 BSC
2.54 BSC
H 0.052 0.095 1.32 2.41
J 0.008 0.015 0.20 0.38
K 0.115 0.135 2.92 3.43
L 0.300 BSC
7.62 BSC
M 0_ 10_ 0_ 10_
N 0.015 0.039 0.39 1.01
MOTOROLA CMOS LOGIC DATA
MC14007UB
35

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