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PDF NCN8026A Data sheet ( Hoja de datos )
| Número de pieza | NCN8026A | |
| Descripción | Compact Low Power Smart Card Interface IC | |
| Fabricantes | ON Semiconductor | |
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NCN8026A
Compact Low Power Smart
Card Interface IC
The NCN8026A is a compact and cost−effective single SIM &
smart card interface IC. It can be used with 1.8 V, 3 V and 5 V IC
cards. The card VCC supply is provided by a built−in very low drop
out and low noise Regulator. The NCN8026A offers enhanced
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performances with low VCC output ripple under load−transient
conditions, very low shutdown current and 1.8 V−to−5 V logic
MARKING
compatibility.
DIAGRAMS
This device is fully compatible with the ISO 7816−3, EMV 4.2,
UICC and related standards including NDS and other STB standards
(Nagravision, Irdeto, Conax ..). It satisfies the requirements specifying
conditional access into Set−Top−Boxes (STB) or Conditional Access
QFN24
MN SUFFIX
CASE 485L
NCN
8026A
ALYWG
G
Modules (CAM).
This smart card interface IC is available in a QFN−24 package
A = Assembly Location
providing all the industry−standard features usually required for STB
smart card interface.
L = Wafer Lot
Y = Year
W = Work Week
Features
• Single IC Card Interface
G = Pb−Free Package
(Note: Microdot may be in either location)
• Fully Compatible with ISO 7816−3, EMV4.2, UICC and Related
Standards Including NDS and Other STB Standards (Nagravision,
Irdeto, Conax...)
• Three Bidirectional Buffered I/O Level Shifters (C4, C7 and C8)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 14 of this data sheet.
• 1.8 V, 3.0 V or 5.0 V $ 5 % Regulated Card Power Supply Such as
ICC ≤ 70 mA with Low VCC Ripple
• Regulator Power Supply: VDDP = 2.7 V to 5.5 V (@ 1.8 V),
3.0 V to 5.5 V (@ 3.0 V) and 4.85 V to 5.5 V (@ 5.0 V)
• Independent Power Supply range on Controller
• Interrupt Signal INT for Card Presence and Faults
Interface such as VDD = 1.6 V to 5.5 V
• Handles Class A, B and C Smart Cards
• Short Circuit Protection on all Card Pins
• Support up to 27 MHz input Clock with Internal
• Chip Select Pin (CS) for Dual Card Operating
• External Under−Voltage Lockout Threshold
Adjustment on VDD (PORADJ Pin)
• Available in One Package Formats: QFN−24
Division Ratio 1/1, 1/2, 1/4 and 1/8 through CLKDIV1
and CLKDIV2
• HBM ESD Protection on Card Pins up to +8 kV
(Human Body Model)
• Activation / Deactivation Sequences (ISO7816
Sequencer)
• Fault Protection Mechanisms Enabling Automatic
Device Deactivation in Case of Overload, Overheating,
• These are Pb−Free Devices
Typical Application
• Pay TV, Set Top Box Decoder with Conditional Access
and Pay−per−View
• Conditional Access Module (CAM / CAS)
• SIM card interface applications (UICC / USIM)
• Point Of Sales and Transaction Terminals
Card Take−off or Power Supply Drop−out (OCP, OTP,
• Electronic Payment and Identification
UVP)
© Semiconductor Components Industries, LLC, 2016
May, 2016 − Rev. 7
1
Publication Order Number:
NCN8026A/D
1 page  
NCN8026A
ATTRIBUTES
Characteristics
ESD protection
Human Body Model (HBM) (Note 1)
Card Pins (card interface pins 4−11)
All Other Pins
Machine Model (MM)
Card Pins (card interface pins 4−11)
All Other Pins
Moisture sensitivity (Note 2) QFN−24
Flammability Rating Oxygen Index: 28 to 34
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latch−up Test
1. Human Body Model (HBM), R = 1500 W, C = 100 pF.
2. For additional information, see Application Note AND8003/D.
Values
8 kV
2 kV
400 V
150 V
Level 1
UL 94 V−0 @ 0.125 in
MAXIMUM RATINGS (Note 3)
Rating
Symbol
Value
Unit
Regulator Power Supply Voltage
Power Supply from Microcontroller Side
External Card Power Supply
VDDP
VDD
CVCC
−0.3 ≤ VDDP ≤ 5.5
−0.3 ≤ VDD ≤ 5.5
−0.3 ≤ CVCC ≤ 5.5
V
V
V
Digital Input Pins
Vin
−0.3 ≤ Vin ≤ VDD
V
Digital Output Pins (I/Ouc, AUX1uc, AUX2uc, INT)
Vout
−0.3 ≤ Vout ≤ VDD
V
Smart card Output Pins
Vout
−0.3 ≤ Vout ≤ CVCC
V
Thermal Resistance Junction−to−Air
QFN−24
RqJA
90 °C/W
Operating Ambient Temperature Range
TA
−40 to +85
°C
Operating Junction Temperature Range
TJ
−40 to +125
°C
Maximum Junction Temperature
TJmax
+125
°C
Storage Temperature Range
Tstg
−65 to + 150
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
3. Maximum electrical ratings are defined as those values beyond which damage to the device may occur at TA = +25°C.
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5
5 Page 
NCN8026A
The clock can also be applied to the card using a RSTIN
mode allowing controlling the clock starting by setting
RSTIN Low (Figure 4). Before running the activation
sequence, that is before setting Low CMDVCC RSTIN is set
High. The following sequence is applied:
− The Smart Card Interface is enable by setting
CMDVCC LOW (RSTIN is High).
− Between t2 (Figure 4) and t5 = 240 ms, RSTIN is reset
to LOW and CCLK will start precisely at this moment
allowing a precise count of clock cycles before toggling
CRST Low to High for ATR (Answer To Reset)
request.
− CRST remains LOW until 240 ms; after t5 = 240 ms
CRST is enabled and is the copy of RSTIN which has
no more control on the clock.
CMDVCC
If controlling the clock with RSTIN is not necessary
(Normal Mode), then CMDVCC can be set LOW with
RSTIN LOW. In that case, CLK will start minimum 2 ms
after the transition on I/O (Figure 5), and to obtain an ATR,
CRST can be set High by RSTIN also about 2 ms after the
clock channel activation (Tact).
The internal activation sequence activates the different
channels according to a specific hardware built−in
sequencing internally defined but at the end the actual
activation sequencing is the responsibility of the application
software and can be redefined by the micro−controller to
comply with the different standards and the different ways
the standards manage this activation (for example light
differences exist between the EMV and the ISO7816
standards).
CVCC
CIO
CCLK
ATR
RSTIN
CRST
t0 t1 t2 t4
t5
~240 ms
Figure 4. Activation Sequence − RSTIN Mode (RSTIN Starting High)
CMDVCC
CVCC
CIO
CCLK
RSTIN
CRST
ATR
t0 t1 t2 t3
t4
Tact
Figure 5. Activation Sequence − Normal Mode
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