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PDF CAV24C32 Data sheet ( Hoja de datos )
| Número de pieza | CAV24C32 | |
| Descripción | 32-Kb I2C CMOS Serial EEPROM | |
| Fabricantes | ON Semiconductor | |
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CAV24C32
32-Kb I2C CMOS Serial
EEPROM
Description
The CAV24C32 is a 32−Kb CMOS Serial EEPROM devices,
internally organized as 4096 words of 8 bits each.
It features a 32−byte page write buffer and supports the Standard
(100 kHz) and Fast (400 kHz) I2C protocol.
External address pins make it possible to address up to eight
CAV24C32 devices on the same bus.
Features
• Automotive Temperature Grade 1 (−40°C to +125°C)
• Supports Standard and Fast I2C Protocol
• 2.5 V to 5.5 V Supply Voltage Range
• 32−Byte Page Write Buffer
• Hardware Write Protection for Entire Memory
• CAV Prefix for Automotive and Other Applications Requiring Site
and Change Control
• Schmitt Triggers and Noise Suppression Filters on I2C Bus Inputs
(SCL and SDA)
• Low Power CMOS Technology
• 1,000,000 Program/Erase Cycles
• 100 Year Data Retention
• SOIC, TSSOP 8−lead, and WLCSP 4−Ball and 5−Ball Packages
• This Device is Pb−Free, Halogen Free/BFR Free, and RoHS
Compliant
VCC
SCL
A2, A1, A0
WP
CAV24C32
SDA
VSS
Figure 1. Functional Symbol
This document contains information on some products that are still under development.
ON Semiconductor reserves the right to change or discontinue these products without
notice.
© Semiconductor Components Industries, LLC, 2016
February, 2016 − Rev. 2
1
www.onsemi.com
WLCSP5
C5A SUFFIX
CASE 567JQ
WLCSP4
SOIC−8
C4C SUFFIX W SUFFIX
CASE 567JY CASE 751BD
TSSOP−8
Y SUFFIX
CASE 948AL
PIN CONFIGURATIONS (Top Views)
123
1
VCC
2
VSS A
VCC VSS
A
B
SCL SDA B
SDA
C
WLCSP4 (C4C)
WP SCL
WLCSP5 (C5A)
1
A0
VCC
A1 WP
A2 SCL
VSS SDA
SOIC (W), TSSOP (Y)
For the location of Pin 1, please consult the
corresponding package drawing.
PIN FUNCTION
Pin Name
A0, A1, A2
Function
Device Address Input
SDA
Serial Data Input/Output
SCL
WP
VCC
VSS
Serial Clock Input
Write Protect Input
Power Supply
Ground
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 12 of this data sheet.
Publication Order Number:
CAV24C32/D
1 page  
SCL FROM
MASTER
CAV24C32
BUS RELEASE DELAY (TRANSMITTER)
18
9
BUS RELEASE DELAY (RECEIVER)
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACK DELAY (≤ tAA)
Figure 4. Acknowledge Timing
ACK SETUP (≥ tSU:DAT)
SCL
tSU:STA
SDA IN
SDA OUT
tF tHIGH tR
tLOW
tLOW
tHD:SDA
tHD:DAT
tSU:DAT
tAA tDH
Figure 5. Bus Timing
tSU:STO
tBUF
WRITE OPERATIONS
Byte Write
To write data to memory, the Master creates a START
condition on the bus and then broadcasts a Slave address
with the R/W bit set to ‘0’. The Master then sends two
address bytes and a data byte and concludes the session by
creating a STOP condition on the bus. The Slave responds
with ACK after every byte sent by the Master (Figure 6). The
STOP starts the internal Write cycle, and while this
operation is in progress (tWR), the SDA output is tri-stated
and the Slave does not acknowledge the Master (Figure 7).
Page Write
The Byte Write operation can be expanded to Page Write,
by sending more than one data byte to the Slave before
issuing the STOP condition (Figure 8). Up to 32 distinct data
bytes can be loaded into the internal Page Write Buffer
starting at the address provided by the Master. The page
address is latched, and as long as the Master keeps sending
data, the internal byte address is incremented up to the end
of page, where it then wraps around (within the page). New
data can therefore replace data loaded earlier. Following the
STOP, data loaded during the Page Write session will be
written to memory in a single internal Write cycle (tWR).
Acknowledge Polling
As soon (and as long) as internal Write is in progress, the
Slave will not acknowledge the Master. This feature enables
the Master to immediately follow-up with a new Read or
Write request, rather than wait for the maximum specified
Write time (tWR) to elapse. Upon receiving a NoACK
response from the Slave, the Master simply repeats the
request until the Slave responds with ACK.
Hardware Write Protection
With the WP pin held HIGH, the entire memory is
protected against Write operations. If the WP pin is left
floating or is grounded, it has no impact on the Write
operation. The state of the WP pin is strobed on the last
falling edge of SCL immediately preceding the 1st data byte
(Figure 9). If the WP pin is HIGH during the strobe interval,
the Slave will not acknowledge the data byte and the Write
request will be rejected.
Delivery State
The CAV24C32 is shipped erased, i.e., all bytes are FFh.
www.onsemi.com
5
5 Page 
CAV24C32
PACKAGE DIMENSIONS
ÈÈÈÈPIN A1
REFERENCE
D
2X 0.05 C
AB
E
2X 0.05 C TOP VIEW
DETAIL A
0.05 C
A2
WLCSP4, 0.76x0.76
CASE 567JY
ISSUE O
DIE COAT
(OPTIONAL)
A3
A2
DETAIL A
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. COPLANARITY APPLIES TO SPHERICAL
CROWNS OF SOLDER BALLS.
MILLIMETERS
DIM MIN MAX
A −−− 0.35
A1 0.0415 0.0715
A2 0.255 REF
A3 0.025 REF
b 0.15 0.16
D 0.76 BSC
E 0.76 BSC
e 0.40 BSC
A
0.05 C
NOTE 3
A1
SIDE VIEW
C
SEATING
PLANE
RECOMMENDED
SOLDERING FOOTPRINT*
A1 PACKAGE
OUTLINE
4X b
0.05 C A B
0.03 C
e
B
A
12
BOTTOM VIEW
e
0.40
PITCH
4X
0.16
0.40
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
www.onsemi.com
11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet CAV24C32.PDF ] | |
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