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PDF 9DBL06 Data sheet ( Hoja de datos )

Número de pieza 9DBL06
Descripción 6-output 3.3V PCIe Zero-Delay Buffer
Fabricantes IDT 
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No Preview Available ! 9DBL06 Hoja de datos, Descripción, Manual

6-output 3.3V PCIe Zero-Delay Buffer
9DBL06
Description
The 9DBL06 devices are 3.3V members of IDT's
Full-Featured PCIe family. The 9DBL06 supports PCIe
Gen1-4 Common Clocked (CC) and PCIe Separate
Reference Independent Spread (SRIS) systems. It offers a
choice of integrated output terminations providing direct
connection to 85or 100transmission lines. The
9DBL06P1 can be factory programmed with a user-defined
power up default SMBus configuration.
Recommended Application
PCIe Gen1-4 clock distribution for Riser Cards, Storage,
Networking, JBOD, Communications, Access Points
Output Features
6 – 1-200 MHz Low-Power (LP) HCSL DIF pairs
9DBL0641 default ZOUT = 100
9DBL0651 default ZOUT = 85
9DBL06P1 factory programmable defaults
Key Specifications
PCIe Gen1-2-3-4 CC compliant in ZDB mode
PCIe Gen2 SRIS compliant in ZDB mode
Supports PCIe Gen2-3 SRIS in fan-out mode
DIF cycle-to-cycle jitter <50ps
DIF output-to-output skew < 50ps
Bypass mode additive phase jitter is 0 ps typical rms for
PCIe
Bypass mode additive phase jitter 160fs rms typ. @
156.25M (1.5M to 10M)
Block Diagram
DATASHEET
Features/Benefits
Direct connection to 100(xx41) or 85(xx51)
transmission lines; saves 24 resistors compared to
standard PCIe devices
149mW typical power consumption (PLL [email protected]);
eliminates thermal concerns
VDDIO allows 30% power savings at optional 1.05V;
maximum power savings
SMBus-selectable features allows optimization to customer
requirements:
control input polarity
control input pull up/downs
– slew rate for each output
– differential output amplitude
– output impedance for each output
– 50, 100, 125MHz operating frequency
Customer defined SMBus power up default can be
programmed into P1 device; allows exact optimization to
customer requirements
OE# pins; support DIF power management
HCSL-compatible differential input; can be driven by
common clock sources
Spread Spectrum tolerant; allows reduction of EMI
Pin/SMBus selectable PLL bandwidth and PLL Bypass;
minimize phase jitter for each application
Outputs blocked until PLL is locked; clean system start-up
Device contains default configuration; SMBus interface not
required for device operation
Three selectable SMBus addresses; multiple devices can
easily share an SMBus segment
Space saving 40-pin 5x5mm VFQFPN; minimal board
space
Note: Default resistors are internal on xx41/xx51 devices. P1 devices have programmable default impedances on an output-by-output basis.
9DBL06 REVISION E 06/14/16
1 ©2016 Integrated Device Technology, Inc.

1 page




9DBL06 pdf
9DBL06 DATASHEET
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 9DBL06. These ratings, which are standard values
for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions
above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating
conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended
operating temperature range.
PARAMETER
SYMBOL
CONDITIONS
Supply Voltage
VDDx
Input Voltage
VIN
Input High Voltage, SMBus VIHSMB
Storage Temperature
Ts
SMBus clock and data pins
Junction Temperature
Tj
Input ESD protection
ESD prot
Human Body Model
1Guaranteed by design and characterization, not 100% tested in production.
2 Operation under these conditions is neither implied nor guaranteed.
3 Not to exceed 4.6V.
MIN
-0.5
-65
2500
TYP
MAX
4.6
VDD+0.5
3.9
150
125
UNITS NOTES
V 1,2
V 1,3
V1
°C 1
°C 1
V1
Electrical Characteristics–Clock Input Parameters
TA = TAMB, Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
Input Crossover Voltage -
DIF_IN
VCROSS
Cross Over Voltage
150
Input Swing - DIF_IN
Input Slew Rate - DIF_IN
VSWING
dv/dt
Differential value
Measured differentially
300
0.4
Input Leakage Current
IIN
VIN = VDD , VIN = GND
Input Duty Cycle dtin Measurement from differential wavefrom
Input Jitter - Cycle to Cycle JDIFIn
Differential Measurement
1 Guaranteed by design and characterization, not 100% tested in production.
2Slew rate measured through +/-75mV window centered around differential zero
-5
45
0
TYP MAX UNITS NOTES
900 mV 1
mV 1
8 V/ns 1,2
5 uA
55 % 1
125 ps 1
Electrical Characteristics–SMBus Parameters
TA = TAMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
SMBus Input Low Voltage VILSMB
VDDSMB = 3.3V
SMBus Input High Voltage VIHSMB
VDDSMB = 3.3V
SMBus Output Low Voltage VOLSMB
@ IPULLUP
SMBus Sink Current
IPULLUP
@ VOL
Nominal Bus Voltage
VDDSMB
SCLK/SDATA Rise Time
tRSMB
(Max VIL - 0.15) to (Min VIH + 0.15)
SCLK/SDATA Fall Time
tFSMB
(Min VIH + 0.15) to (Max VIL - 0.15)
SMBus Operating
Frequency
fSMB
SMBus operating frequency
1 Guaranteed by design and characterization, not 100% tested in production.
2. The device must be powered up for the SMBus to function.
3. The differential input clock must be running for the SMBus to be active
2.1
4
2.7
TYP
MAX
0.8
3.6
0.4
3.6
1000
300
500
UNITS NOTES
V
V
V
mA
V
ns 1
ns 1
kHz 2,3
REVISION E 06/14/16
5 6-OUTPUT 3.3V PCIE ZERO-DELAY BUFFER

5 Page





9DBL06 arduino
9DBL06 DATASHEET
SMBus Table: Output Enable Register 1
Byte 0
Name
Control Function
Type
0
1 Default
Bit 7
Bit 6
DIF OE5
DIF OE4
Output Enable
Output Enable
RW
RW
See B11[1:0]
Pin Control
Pin Control
1
1
Bit 5
Reserved
0
Bit 4
DIF OE3
Output Enable
RW
Pin Control
1
Bit 3
DIF OE2
Output Enable
RW See B11[1:0]
Pin Control
1
Bit 2
DIF OE1
Output Enable
RW
Pin Control
1
Bit 1
Reserved
0
Bit 0
DIF OE0
Output Enable
RW See B11[1:0]
Pin Control
1
1. A low on these bits will overide the OE# pin and force the differential output to the state indicated by B11[1:0] (Low/Low default)
SMBus Table: PLL Operating Mode and Output Amplitude Control Register
Byte 1
Name
Control Function
Type
0
1
Bit 7
Bit 6
PLLMODERB1
PLLMODERB0
PLL Mode Readback Bit 1
PLL Mode Readback Bit 0
R
R
See PLL Operating Mode Table
Bit 5
PLLMODE_SWCNTRL
Enable SW control of PLL Mode RW
Values in B1[7:6]
set PLL Mode
Values in B1[4:3]
set PLL Mode
Bit 4
Bit 3
PLLMODE1
PLLMODE0
PLL Mode Control Bit 1
PLL Mode Control Bit 0
RW1
RW1
See PLL Operating Mode Table
Bit 2
Reserved
Bit 1
Bit 0
AMPLITUDE 1
AMPLITUDE 0
Controls Output Amplitude
RW
RW
00 = 0.6V
10 = 0.75V
01= 0.68V
11 = 0.85V
1. B1[5] must be set to a 1 for these bits to have any effect on the part.
Default
Latch
Latch
0
0
0
1
1
0
SMBus Table: Slew Rate Control Register
Byte 2
Name
Control Function
Bit 7
SLEWRATESEL DIF5
Slew rate selection
Bit 6
SLEWRATESEL DIF4
Slew rate selection
Bit 5
Reserved
Bit 4
SLEWRATESEL DIF3
Slew rate selection
Bit 3
SLEWRATESEL DIF2
Slew rate selection
Bit 2
SLEWRATESEL DIF1
Slew rate selection
Bit 1
Reserved
Bit 0
SLEWRATESEL DIF0
Slew rate selection
Note: See "Low-Power HCSL Outputs" table for slew rates.
Type
RW
RW
RW
RW
RW
RW
0
Slow Setting
Slow Setting
Slow Setting
Slow Setting
Slow Setting
Slow Setting
1
Fast Setting
Fast Setting
Fast Setting
Fast Setting
Fast Setting
Fast Setting
Default
1
1
1
1
1
1
1
1
SMBus Table: Slew Rate Control Register
Byte 3
Name
Control Function
Bit 7
Reserved
Bit 6
Bit 5
FREQ_SEL_EN
Reserved
Enable SW selection of
frequency
Bit 4
FSEL1
Freq. Select Bit 1
Bit 3
FSEL0
Freq. Select Bit 0
Bit 2
Bit 1
Bit 0
SLEWRATESEL FB
Reserved
Reserved
Adjust Slew Rate of FB
1. B3[5] must be set to a 1 for these bits to have any effect on the part.
Type
RW
RW1
RW1
RW
01
SW frequency
SW frequency
change disabled change enabled
00 = 100M, 10 = 125M
01 = 50M, 11= Reserved
Slow Setting
Fast Setting
Default
1
1
0
0
0
1
1
1
Byte 4 is Reserved
REVISION E 06/14/16
11 6-OUTPUT 3.3V PCIE ZERO-DELAY BUFFER

11 Page







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