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PDF 9DB423B Data sheet ( Hoja de datos )

Número de pieza 9DB423B
Descripción Four Output Differential Buffer
Fabricantes IDT 
Logotipo IDT Logotipo



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DATASHEET
Four Output Differential Buffer for PCIe Gen 1, Gen 2 and QPI
9DB423B
Recommended Application:
DB400Q compatible part with PCIe Gen1, Gen 2 and QPI
support
General Description:
The ICS9DB423 is compatible with the Intel DB400Q Differential
Buffer Specification. This buffer provides 4 PCI-Express SRC or
4 QPI clocks. The ICS9DB423 is driven by a differential output
pair from a CK410B+ or CK509B main clock generator.
Key Specifications
• Output cycle-cycle jitter < 50ps.
• Output to Output skew <50ps
• Phase jitter: PCIe Gen1 < 86ps peak to peak
• Phase jitter: PCIe Gen2 < 3.0/3.1ps rms
• Phase jitter: QPI < 0.5ps rms
• RoHS compliant packaging
Features/Benefits
• Spread spectrum modulation tolerant, 0 to -0.5% down
spread and +/- 0.25% center spread.
• Supports undriven differential outputs in Power Down and
DIF_STOP# modes for power management.
Output Features
• 4 - 0.7V current-mode differential output pairs
• Supports zero delay buffer mode and fanout mode
• Bandwidth programming available
• 50-133 MHz operation in PLL mode
• 33-400 MHz operation in Bypass mode
Funtional Block Diagram
OE(6,1)
2
SRC_IN
SRC_IN#
SPREAD
COMPATIBLE
PLL
4
M
U
STOP
X LOGIC
DIF(6,5,2,1)
PD
BYPASS#_133_100
HIGH_BW#
DIF_STOP#
SDATA
SCLK
CONTROL
LOGIC
IREF
Note: Polarities shown for OE_INV = 0.
IDT® Four Output Differential Buffer for PCIe and Gen 1, Gen 2 and QPI
1
1437B - 02/04/10

1 page




9DB423B pdf
9DB423B
Four Output Differential Buffer for PCIe for Gen 1, Gen 2 and QPI
Absolute Max
Symbol
VDD_A
VDD_In
VIL
VIH
Ts
Tambient
Tcase
ESD prot
Parameter
3.3V Core Supply Voltage
3.3V Logic Supply Voltage
Input Low Voltage
Input High Voltage
Storage Temperature
Ambient Operating Temp
Case Temperature
Input ESD protection
human body model
Min
GND-0.5
-65
0
2000
Max
4.6
4.6
VDD+0.5V
150
70
115
Units
V
V
V
V
°C
°C
°C
V
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN TYP
Input High Voltage
VIH
3.3 V +/-5%
Input Low Voltage
VIL
3.3 V +/-5%
Input High Current
IIH
VIN = VDD
Input Low Current
IIL1 VIN = 0 V; Inputs with no pull-up resistors
IIL2 VIN = 0 V; Inputs with pull-up resistors
Operating Supply Current
Powerdown Current
IDD3.3OP
IDD3.3PD
Full Active, CL = Full load;
all diff pairs driven
all differential pairs tri-stated
Input Frequency
FiPLL
FiPLL
PCIe Mode (Bypass/133/100= 1)
QPI Mode (Bypass/133/100= M)
FiBYPASS
Bypass Mode (Bypass/133/100= 0)
Pin Inductance
Lpin
Capacitance
CIN
CINSRC_IN
Logic Inputs, except SRC_IN
SRC_IN differential clock inputs
PLL Bandwidth
COUT
BW
Output pin capacitance
-3dB point in High BW Mode
-3dB point in Low BW Mode
PLL Jitter Peaking
tJPEAK
Peak Pass band Gain
Clk Stabilization
TSTAB
From VDD Power-Up and after input clock
stabilization or de-assertion of PD# to 1st clock
Input SS Modulation
Frequency
fMODIN
Allowable Frequency
(Triangular Modulation)
OE# Latency
tLATOE#
DIF start after OE# assertion
DIF stop after OE# deassertion
Tdrive_DIF_Stop#
tDRVSTP
DIF output enable after
DIF_Stop# de-assertion
Tdrive_PD#
tDRVPD
DIF output enable after
PD# de-assertion
Tfall tF Fall time of PD# and DIF_Stop#
Trise
tR Rise time of PD# and DIF_Stop#
SMBus Voltage
VMAX
Maximum input voltage
Low-level Output Voltage
VOL
@ IPULLUP
Current sinking at VOL
SCLK/SDATA
Clock/Data Rise Time
IPULLUP
tRSMB
(Max VIL - 0.15) to
(Min VIH + 0.15)
SCLK/SDATA
Clock/Data Fall Time
tFSMB
(Min VIH + 0.15) to
(Max VIL - 0.15)
SMBus Operating Frequency fMAXSMB
Maximum SMBus operating frequency
1Guaranteed by design and characterization, not 100% tested in production.
2See timing diagrams for timing requirements.
3Time from deassertion until outputs are >200 mV
4SRC_IN input
5The differential input clock must be running for the SMBus to be active
2
GND - 0.3
-5
-5
-200
50
67
33
1.5
1.5
2
0.7
30
1
4
100.00
133.33
3
1
1.5
MAX
VDD + 0.3
0.8
5
200
60
6
110
140
400
7
5
2.7
6
4
1.4
2
1
33
3
10
300
5
5
5.5
0.4
1000
300
100
UNITS NOTES
V1
V1
uA 1
uA 1
uA
mA
mA
mA
MHz
1
1
1
1
1
MHz
MHz
nH
pF
1
1
1
1
pF
pF
MHz
MHz
dB
1,4
1
1
1
1
ms 1,2
kHz 1
cycles 1,3
ns 1,3
us 1,3
ns 1
ns 2
V1
V1
mA 1
ns 1
ns 1
kHz 1,5
IDT® Four Output Differential Buffer for PCIe Gen 1, Gen 2 and QPI
1437B - 02/04/10
5

5 Page





9DB423B arduino
9DB423B
Four Output Differential Buffer for PCIe for Gen 1, Gen 2 and QPI
General SMBus serial interface information for the 9DB423B
How to Write:
Controller (host) sends a start bit.
• Controller (host) sends the write address DC (h)
• ICS clock will acknowledge
• Controller (host) sends the beginning byte location = N
• ICS clock will acknowledge
• Controller (host) sends the data byte count = X
• ICS clock will acknowledge
• Controller (host) starts sending Byte N through
Byte N + X -1
• ICS clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the write address DC (h)
• ICS clock will acknowledge
• Controller (host) sends the begining byte
location = N
• ICS clock will acknowledge
• Controller (host) will send a separate start bit.
• Controller (host) sends the read address DD
(h)
• ICS clock will acknowledge
• ICS clock will send the data byte count = X
• ICS clock sends Byte N + X -1
• ICS clock sends Byte 0 through byte X (if X(h)
was written to byte 8).
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host)
T starT bit
ICS (Slave/Receiver)
Slave Address DC(h)
WR WRite
ACK
Beginning Byte = N
ACK
Data Byte Count = X
ACK
Beginning Byte N
ACK
Byte N + X - 1
P stoP bit
ACK
Index Block Read Operation
Controller (Host)
T starT bit
ICS (Slave/Receiver)
Slave Address DC(h)
WR WRite
Beginning Byte = N
RT Repeat starT
ACK
ACK
Slave Address DD(h)
RD ReaD
ACK
ACK
ACK
Data Byte Count = X
Beginning Byte N
IDT® Four Output Differential Buffer for PCIe Gen 1, Gen 2 and QPI
11
N Not acknowledge
P stoP bit
Byte N + X - 1
1437B - 02/04/10

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