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PDF 9FGU0431 Data sheet ( Hoja de datos )

Número de pieza 9FGU0431
Descripción 4 O/P 1.5V PCIe Gen1-2-3 Clock Generator
Fabricantes IDT 
Logotipo IDT Logotipo



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4 O/P 1.5V PCIe Gen1-2-3 Clock Generator
9FGU0431
DATASHEET
Description
The 9FGU0431 is a member of IDT's 1.5V Ultra-Low-Power
PCIe clock family. The device has 4 output enables for clock
management, 2 different spread spectrum levels in addition to
spread off and 2 selectable SMBus addresses.
Recommended Application
1.5V PCIe Gen1-2-3 Clock Generator
Output Features
4 - 100MHz Low-Power (LP) HCSL DIF pair
1 - 1.5V LVCMOS REF output w/Wake-On-LAN (WOL)
support
Key Specifications
DIF cycle-to-cycle jitter <50ps
DIF output-to-output skew <50ps
DIF phase jitter is PCIe Gen1-2-3 compliant
REF phase jitter is < 3.0ps RMS
Block Diagram
Features/Benefits
LP-HCSL outputs; save 8 resistors compared to standard
PCIe device
39mW typical power consumption; reduced thermal
concerns
OE# pins; support DIF power management
Programmable Slew rate for each output; allows tuning for
various line lengths
Programmable output amplitude; allows tuning for various
application environments
DIF outputs blocked until PLL is locked; clean system
start-up
Selectable 0%, -0.25% or -0.5% spread on DIF outputs;
reduces EMI
External 25MHz crystal; supports tight ppm with 0 ppm
synthesis error
Configuration can be accomplished with strapping pins;
SMBus interface not required for device control
Selectable SMBus addresses; multiple devices can easily
share an SMBus segment
3.3V tolerant SMBus interface works with legacy controllers
Space saving 32-pin 5x5 mm VFQFPN; minimal board
space
XIN/CLKIN_25
X2
vOE(3:0)#
OSC
REF1.5
vSADR
vSS_EN_tri
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
CONTROL
LOGIC
SS Capable PLL
DIF3
DIF2
DIF1
DIF0
9FGU0431 OCTOBER 18, 2016
1 ©2016 Integrated Device Technology, Inc.

1 page




9FGU0431 pdf
9FGU0431 DATASHEET
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 9FGU0431. These ratings, which are standard
values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other
conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the
recommended operating temperature range.
PARAMETER
SYMBOL
CONDITIONS
Supply Voltage
VDDxx
Applies to all VDD pins
Input Voltage
VIN
Input High Voltage, SMBus VIHSMB
Storage Temperature
Ts
SMBus clock and data pins
Junction Temperature
Tj
Input ESD protection ESD prot
Human Body Model
1Guaranteed by design and characterization, not 100% tested in production.
2 Operation under these conditions is neither implied nor guaranteed.
3 Not to exceed 2.5V.
MIN
-0.5
-0.5
-65
2000
TYP
MAX
2
VDD+0.5V
3.3V
150
125
UNITS
V
V
V
°C
°C
V
NOTES
1,2
1,3
1
1
1
1
Electrical Characteristics–Current Consumption
TA = TAMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS NOTES
Operating Supply Current
IDDAOP
IDDOP
VDDA, All outputs active @100MHz
All VDD, except VDDA, All outputs active
@100MHz
6.2 9
20 27
mA
mA
Wake-on-LAN Current
(CKPWRGD_PD# = '0'
Byte 3, bit 5 = '1')
IDDAPD
IDDPD
VDDA, DIF outputs off, REF output running
All VDD, except VDDA,
DIF outputs off, REF output running
0.4 1 mA
4.3 6.5 mA
2
2
Powerdown Current
(CKPWRGD_PD# = '0'
Byte 3, bit 5 = '0')
IDDAPD
VDDA, all outputs off
IDDPD All VDD, except VDDA and VDDIO, all outputs off
0.4
0.4
1 Guaranteed by design and characterization, not 100% tested in production.
2 This is the current required to have the REF output running in Wake-on-LAN mode (Byte 3, bit 5 = 1)
1
1
mA
mA
Electrical Characteristics–DIF Output Duty Cycle, Jitter, and Skew Characteristics
TA = TAMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS NOTES
Duty Cycle
tDC Measured differentially, PLL Mode
Skew, Output to Output
tsk3
Averaging on, VT = 50%
Jitter, Cycle to cycle
tjcyc-cyc
1Guaranteed by design and characterization, not 100% tested in production.
2 Measured from differential waveform
45 50 55
32 50
16 50
%
ps
ps
1,2
1
1,2
OCTOBER 18, 2016
5 4 O/P 1.5V PCIE GEN1-2-3 CLOCK GENERATOR

5 Page





9FGU0431 arduino
9FGU0431 DATASHEET
SMBus Table: Revision and Vendor ID Register
Byte 5
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
RID3
RID2
RID1
RID0
VID3
VID2
VID1
VID0
Control Function
Revision ID
VENDOR ID
Type
R
R
R
R
R
R
R
R
01
A rev = 0000
0001 = IDT
Default
0
0
0
0
0
0
0
1
SMBus Table: Device Type/Device ID
Byte 6
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Device Type1
Device Type0
Device ID5
Device ID4
Device ID3
Device ID2
Device ID1
Device ID0
Control Function
Device Type
Device ID
Type
R
R
R
R
R
R
R
R
01
00 = FGx, 01 = DBx ZDB/FOB,
10 = DMx, 11= DBx FOB
000100 binary or 04 hex
Default
0
0
0
0
0
1
0
0
SMBus Table: Byte Count Register
Byte 7
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BC4
BC3
BC2
BC1
BC0
Control Function
Reserved
Reserved
Reserved
Byte Count Programming
Type
0
1
RW
RW Writing to this register will configure how
RW many bytes will be read back, default is
RW = 8 bytes.
RW
Default
0
0
0
0
1
0
0
0
Recommended Crystal Characteristics (3225 package)
PARAMETER
Frequency
Resonance Mode
Frequency Tolerance @ 25°C
Frequency Stability, ref @ 25°C Over
Operating Temperature Range
Temperature Range (commerical)
Temperature Range (industrial)
Equivalent Series Resistance (ESR)
Shunt Capacitance (CO)
Load Capacitance (CL)
Drive Level
Aging per year
Notes:
1. FOX 603-25-150.
2. For I-temp, FOX 603-25-261.
VALUE
25
Fundamental
±20
±20
0~70
-40~85
50
7
8
0.3
±5
UNITS
MHz
-
PPM Max
NOTES
1
1
1
PPM Max
°C
°C
Max
pF Max
pF Max
mW Max
PPM Max
1
1
2
1
1
1
1
1
OCTOBER 18, 2016
11 4 O/P 1.5V PCIE GEN1-2-3 CLOCK GENERATOR

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