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PDF ICS9FG1201H Data sheet ( Hoja de datos )

Número de pieza ICS9FG1201H
Descripción Frequency Generator
Fabricantes IDT 
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DATASHEET
Frequency Generator for CPU, PCIe Gen1* & Fully Buffered
DIMM Clocks
ICS9FG1201H
Description
Features/Benefits
ICS9FG1201 follows the Intel DB1200G Differential Buffer
Specification. This buffer provides 12 output clocks for CPU Host
Bus, PCI Express, or Fully Buffered DIMM applications. The outputs
are configured with two groups. Both groups (DIF 9:0) and (DIF
11:10) can be equal to or have a gear ratio to the input clock. A
differential CPU clock from a CK410 or CK410B main clock generator,
such as the ICS954101 or ICS932S401, drives the ICS9FG1201.
ICS9FG1201 can provide outputs up to 400MHz.
Power up default is all outputs in 1:1 mode
DIF_(9:0) can be “gear-shifted” from the input CPU Host
Clock
DIF_(11:10) can be “gear-shifted” from the input CPU Host
Clock
Spread spectrum compatible
Supports output clock frequencies up to 400 MHz
• 8 Selectable SMBus addresses
• SMBus address determines PLL or Bypass mode
Key Specifications
• DIF output cycle-to-cycle jitter < 50ps
• DIF output-to-output skew < 50ps within a group
• DIF output-to-output skew < 100ns across all outputs
• 56-pin SSOP/TSSOP package
• Available in RoHS compliant packaging
Funtional Block Diagram
OE#
OE(9:0)#
10
SPREAD
COMPATIBLE
PLL
CLK_IN
CLK_IN#
SPREAD
COMPATIBLE
PLL
HIGH_BW#
FS_A_410
VTT_PWRGD#/PD
SMB_A0
SMB_A1
SMB_A2_PLLBYP#
SMBDAT
SMBCLK
CONTROL
LOGIC
GEAR
SHIFT
LOGIC
STOP
LOGIC
2
DIF(11:10)
GEAR
SHIFT
LOGIC
STOP
LOGIC
10
DIF(9:0)
IREF
IDTTM/ICSTM Frequency Generator for CPU, PCIe Gen1* & Fully Buffered DIMM Clocks
1
ICS9FG1201H 10/22/07

1 page




ICS9FG1201H pdf
ICS9FG1201H
Frequency Generator for CPU, PCIe Gen1* & Fully Buffered DIMM Clocks
ICS9FG1201 Programmable Gear Ratios
SMBus
Byte 0
Input Output Gear Ratio
(m) (n)
(n/m)
Input (CPU FSB) and Output
Frequencies (MHz)
200.0 266.7 320.0 333.3 400.0
00000
00001
00010
00011
00100
00101
00110
3
5
12
2
5
8
3
1
2
5
1
3
5
2
0.333
0.400
0.417
0.500
0.600
0.625
0.667
66.7
80.0
83.3
100.0
120.0
125.0
133.3
88.9
106.7
111.1
133.3
160.0
166.7
177.8
106.7
128.0
133.3
160.0
192.0
200.0
213.3
111.1
133.3
138.9
166.7
200.0
208.3
222.2
133.3
160.0
166.7
200.0
240.0
250.0
266.7
00111 4
3
0.750 150.0 200.0 240.0 250.0 300.0
01000
01001
01010
01011
01100
01101
01110
01111
6
1
5
4
3
2
3
1
5
1
6
5
4
3
5
2
0.833
1.000
1.200
1.250
1.333
1.500
1.667
2.000
166.7
200.0
240.0
250.0
266.7
300.0
333.3
400.0
222.2
266.7
320.0
333.3
355.6
400.0
NA
NA
266.7
320.0
384.0
400.0
NA
NA
NA
NA
277.8
333.3
400.0
NA
NA
NA
NA
NA
333.3
400.0
NA
NA
NA
NA
NA
NA
CLK IN (CPU FSB) Frequency (MHz)
100 133.33 160 166.67
10000
10001
10010
10011
3
5
12
2
1
2
5
1
0.333
0.400
0.417
0.500
NA 53.3
NA 55.6
50.0 66.7
64.0
66.7
80.0
66.7
69.4
83.3
10100
10101
10110
5
8
3
3
5
2
0.600
0.625
0.667
60.0 80.0
62.5 83.3
66.7 88.9
96.0
100.0
106.7
100.0
104.2
111.1
10111 5
4
0.800 80.0 106.7 128.0 133.3
11000 6
5
0.833
NA 111.1 133.3 138.9
11001
11010
11011
1
5
4
1
6
5
1.000
1.200
1.250
100.0 133.3
120.0 160.0
125.0 166.7
160.0
192.0
200.0
166.7
200.0
208.3
11100
11101
11110
11111
3
2
3
1
4
3
5
2
1.333
1.500
1.667
2.000
133.3
150.0
166.7
200.0
177.8
200.0
222.2
266.7
213.3
266.7
320.0
222.2
277.8
333.3
Note: Lines in BOLD are Power-up defaults for FS_A_410 = 0 and 1 respectively.
Shaded areas are shown for reference only and are not necessarily valid operating points
IDTTM/ICSTM Frequency Generator for CPU, PCIe Gen1* & Fully Buffered DIMM Clocks
5
ICS9FG1201H 10/22/07

5 Page





ICS9FG1201H arduino
ICS9FG1201H
Frequency Generator for CPU, PCIe Gen1* & Fully Buffered DIMM Clocks
SMBus Table: Gear PLL Frequency Control Register
Byte 12 Pin #
Name
Control Function Type
Bit 7
-
Gear PLL N Div7
RW
Bit 6
-
Gear PLL N Div6
RW
Bit 5
Bit 4
Bit 3
-
-
-
Gear PLL N Div5
Gear PLL N Div4
Gear PLL N Div3
RW
N Divider Programming RW
bits RW
Bit 2
-
Gear PLL N Div2
RW
Bit 1
-
Gear PLL N Div1
RW
Bit 0
-
Gear PLL N Div0
RW
01
See 9FG1201H M/N
programming Table
PWD
X
X
X
X
X
X
X
X
SMBusTable: Gear PLL Output Divider Register
Byte 13 Pin #
Name
Control Function Type
Bit 7
RESERVED
Bit 6
RESERVED
Bit 5
RESERVED
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
GoutDiv 3
GoutDiv 2
GoutDiv 1
GoutDiv 1
RESERVED
Gear Output Divider
RW
RW
RW
RW
01
See Gear Output Divider
Table
PWD
0
0
0
0
X
X
X
X
SMBusTable: Reserved Register
Byte 14 Pin #
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Control Function Type
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
0
1 PWD
0
0
0
0
0
0
0
0
SMBusTable: Reserved Register
Byte 15 Pin #
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Control Function Type
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
0
1 PWD
0
0
0
0
0
0
0
0
IDTTM/ICSTM Frequency Generator for CPU, PCIe Gen1* & Fully Buffered DIMM Clocks
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ICS9FG1201H 10/22/07

11 Page







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