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PDF 8SLVP2108 Data sheet ( Hoja de datos )

Número de pieza 8SLVP2108
Descripción LVPECL Output Fanout Buffer
Fabricantes IDT 
Logotipo IDT Logotipo



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No Preview Available ! 8SLVP2108 Hoja de datos, Descripción, Manual

Low Phase Noise, Dual 1-to-8, 3.3V,
2.5V LVPECL Output Fanout Buffer
8SLVP2108
Datasheet
General Description
The 8SLVP2108 is a high-performance differential dual 1:8
LVPECL fanout buffer. The device is designed for the fanout of
high-frequency, very low additive phase-noise clock and data
signals. The 8SLVP2108 is characterized to operate from a 3.3V or
2.5V power supply. Guaranteed output-to-output and part-to-part
skew characteristics make the 8SLVP2108 ideal for those clock
distribution applications demanding well-defined performance and
repeatability. Two independent buffers with eight low skew outputs
each are available. The integrated bias voltage references enable
easy interfacing of single-ended signals to the device inputs. The
device is optimized for low power consumption and low additive
phase noise.
Block Diagram
PCLKA
nPCLKA
VCC
VREFA
Voltage
Reference
PCLKB
nPCLKB
VCC
VREFB
Voltage
Reference
QA0
nQA0
QA1
nQA1
QA2
nQA2
 
 
 
 
QA7
nQA7
QB0
nQB0
QB1
nQB1
QB2
nQB2
 
 
 
 
QB7
nQB7
Features
Two 1:8, low skew, low additive jitter LVPECL fanout buffers
Two differential clock inputs
Differential PCLKA, nPCLKA and PCLKB, nPCLKB pairs can
accept the following differential input levels: LVDS, LVPECL,
CML
Differential PCLKA, nPCLKA and PCLKB, nPCLKB pairs can
also accept single-ended LVCMOS levels. See Applications
section Wiring the Differential Input Levels to Accept
Single-ended Levels (Figure 1A and Figure 1B).
Maximum input clock frequency: 2GHz
Output bank skew: 15ps (typical)
Propagation delay: 390ps (maximum)
Low additive phase jitter, RMS: 54fs (maximum)
(fREF = 156.25MHz, VPP = 1V, 12kHz – 20MHz, VCC = 3.3V)
Full 3.3V and 2.5V supply voltage
Maximum device current consumption (IEE): 143mA
Available in Lead-free (RoHS 6), 48-Lead VFQFN package
Supports case temperature 105°C operations
-40°C to 85°C ambient operating temperature
Pin Assignment
VCC
QB3
nQB3
QB4
nQB4
QB5
nQB5
QB6
nQB6
QB7
nQB7
VCC
36 35 34 33 32 31 30 29 28 27 26 25
37 24
38 23
39 22
40 8SLVP2108 21
41 48-lead VFQFN 20
42 7mm x 7mm x 0.8mm 19
43 package body 18
44
45
NL Package
17
16
46 Top View 15
47 14
48 13
1 2 3 4 5 6 7 8 9 10 11 12
VCC
nQA4
QA4
nQA3
QA3
nQA2
QA2
nQA1
QA1
nQA0
QA0
VCC
©2016 Integrated Device Technology, Inc.
1
Revision B, November 21, 2016

1 page




8SLVP2108 pdf
8SLVP2108 Datasheet
AC Electrical Characteristics
Table 4A. AC Electrical Characteristics, VCC = 3.3V ± 5% or 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum Typical
fREF
V/t
Input Frequency
Input Edge Rate
PCLKA, nPCLKA and PCLKB, nPCLKB
PCLKA, nPCLKA and PCLKB, nPCLKB
1.5
PCLKA, nPCLKA to any QAx, nQAx or
tPD
Propagation Delay; NOTE 1
PCLKB, nPCLKB to any QBx, nQBx for
120
255
VPP=0.1V or 0.3V
tsk(o)
Output Skew; NOTE 2, 3
29
tsk(b)
Output Bank Skew; NOTE 3, 4
15
tsk(p)
Pulse Skew
4
tsk(pp)
Part-to-Part Skew; NOTE 3, 5
70
tJIT, SP
Spurious Suppression,
Coupling from QA7 to QB0
tR / tF
Output Rise/ Fall Time;
NOTE 6
fQB0 = 500MHz, VPP(PCLKB) = 0.15V,
VCMR(PCLKB) = 1V;
fQA7 = 62.5MHz, VPP(PCLKA) = 1V,
VCMR(PCLKA) = 1V
fQB0 = 500MHz, VPP(PCLKB) = 0.15V,
VCMR(PCLKB) = 1V;
fQA7 = 15.625MHz, VPP(PCLKA) = 1V,
VCMR(PCLKA) = 1V
20% to 80%
-55
-65
60 100
VPP
VCMR
Differential Input Voltage;
NOTE 7, 8
Common Mode Input Voltage;
NOTE 7, 8, 9
fREF < 1.5GHz
fREF 1.5GHz
0.1
0.2
1.0
VO(pp)
Output Voltage Swing,
Peak-to-Peak
VDIFF_OUT
Differential Output Voltage
Swing, Peak-to-Peak
fREF 2GHz, VCC = 2.5V ± 5%
fREF 2GHz, VCC = 3.3V ± 5%
fREF 2GHz, VCC = 2.5V ± 5%
fREF 2GHz, VCC = 3.3V ± 5%
0.29 0.46
0.31 0.48
0.58 0.92
0.62 0.96
Maximum
2
390
63
43
25
154
165
1.5
1.5
VCC – 0.3
0.63
0.67
1.26
1.34
Units
GHz
V/ns
ps
ps
ps
ps
ps
dB
dB
ps
V
V
V
V
V
V
V
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Measured from the differential input crosspoint to the differential output crosspoint.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential crosspoints.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Defined as skew within a bank of outputs at the same supply voltage and with equal load conditions. Measured at the differential
crosspoints.
NOTE 5: Defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and
with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential crosspoints.
NOTE 6: Characterized with input signal meeting the input edge rate minimum specification.
NOTE 7: For single-ended LVCMOS input applications, please refer to the Applications Information, Wiring the Differential Input to Accept
Single-ended Levels, Figures 1A and 1B.
NOTE 8: VIL should not be less than -0.3V. VIH should not be higher than VCC.
NOTE 9: Common mode input voltage is defined at the crosspoint.
©2016 Integrated Device Technology, Inc.
5
Revision B, November 21, 2016

5 Page





8SLVP2108 arduino
8SLVP2108 Datasheet
3.3V LVPECL Clock Input Interface
The PCLK /nPCLK accepts LVPECL, LVDS and other differential
signals. Both differential signals must meet the VPP and VCMR input
requirements. Figures 2A to 2C show interface examples for the
PCLK/ nPCLK input driven by the most common driver types. The
input interfaces suggested here are examples only. If the driver is
from another vendor, use their termination recommendation. Please
consult with the vendor of the driver component to confirm the driver
termination requirements.
3.3V
LVPECL
Zo = 50Ω
Zo = 50Ω
3.3V
R3
125Ω
R4
125Ω
3.3V
PCLK
nPCLK
LVPECL
R1 R2
84Ω 84Ω
Input
Figure 2A. PCLK/nPCLK Input Driven by a
3.3V LVPECL Driver
Figure 2B. PCLK/nPCLK Input Driven by a
3.3V LVPECL Driver with AC Couple
3.3V
LVDS
Zo = 50
Zo = 50
3.3V
R1
100
PCLK
nPCLK
LVPECL
Input
Figure 2C. PCLK/nPCLK Input Driven by a
3.3V LVDS Driver
©2016 Integrated Device Technology, Inc.
11
Revision B, November 21, 2016

11 Page







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