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PDF IDT8SLVP1212I Data sheet ( Hoja de datos )
| Número de pieza | IDT8SLVP1212I | |
| Descripción | LVPECL Output Fanout Buffer | |
| Fabricantes | IDT | |
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Low Phase Noise, 1-to-12, 3.3V, 2.5V
LVPECL Output Fanout Buffer
IDT8SLVP1212I
DATASHEET
General Description
The IDT8SLVP1212I is a high-performance, 12 output differential
LVPECL fanout buffer. The device is designed for the fanout of
high-frequency, very low additive phase-noise clock and data signals.
The IDT8SLVP1212I is characterized to operate from a 3.3V and
2.5V power supply. Guaranteed output-to-output and part-to-part
skew characteristics make the IDT8SLVP1212I ideal for those clock
distribution applications demanding well-defined performance and
repeatability. Two selectable differential inputs and twelve low skew
outputs are available. The integrated bias voltage generators enables
easy interfacing of single-ended signals to the device inputs. The
device is optimized for low power consumption and low additive
phase noise.
Block Diagram
PCLK0
nPCLK0
VCC
PCLK1
nPCLK1
VCC
fREF
SEL
VREF
Voltage
Reference
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
Q6
nQ6
Q7
nQ7
Q8
nQ8
Q9
nQ9
Q10
nQ10
Q11
nQ11
Features
• Twelve low skew, low additive jitter LVPECL outputs
• Two selectable, differential clock inputs
• Differential pairs can accept the following differential input
levels: LVDS, LVPECL, CML
• Maximum input clock frequency: 2GHz
• LVCMOS interface levels for the control input (input select)
• Output skew: 33ps (maximum)
• Propagation delay: 550ps (maximum)
• Low additive phase jitter, RMS at fREF = 156.25MHz, VPP = 1V,
12kHz-20MHz: 60fs (maximum)
• Full 3.3V and 2.5V supply voltage
• Device current consumption (IEE): 131mA (maximum)
• Available in Lead-free (RoHS 6), 40-Lead VFQFN package
• -40°C to 85°C ambient operating temperature
• Differential PCLK0, nPCLK0 and PCLK1, nPCLK1 pairs can also
accept single-ended LVCMOS levels. See Applications section
Wiring the Differential Input Levels to Accept Single-ended Levels
(Figure 1A and Figure 1B)
Pin Assignment
VCC
Q8
nQ8
Q9
nQ9
Q10
nQ10
Q11
nQ11
VCC
30 29 28 27 26 25 24 23 22 21
31 20
32 19
33 18
34 17
35 16
36 15
37 14
38 13
39 12
40 11
1 2 3 4 5 6 7 8 9 10
VCC
nQ3
Q3
nQ2
Q2
nQ1
Q1
nQ0
Q0
VCC
IDT8SLVP1212I
40-lead VFQFN
6mm x 6mm x 0.925mm package body,
2.9mm x 2.9mm E-Pad size
NL Package, Top View
IDT8SLVP1212ANLGI REVISION A JANUARY 28, 2014
1
©2014 Integrated Device Technology, Inc.
1 page  
IDT8SLVP1212I Data Sheet
LOW PHASE NOISE, 1-TO-12, 3.3V, 2.5V LVPECL OUTPUT FANOUT BUFFER
AC Electrical Characteristics
Table 5. AC Electrical Characteristics, VCC = 3.3V ± 5% or 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum Typical
fREF
Input
PCLK[0:1],
Frequency nPCLK[0:1]
V/t
Input
PCLK[0:1],
Edge Rate nPCLK[0:1]
1.5
tPD Propagation Delay; NOTE 1
MUX_ISOLATION MUX Isolation
tsk(o)
Output Skew; NOTE 2, 3
PCLKx, nPCLKx to any Qx, nQx
for VPP = 0.1V or 0.3V
fREF = 100MHz
230
360
70
17
tsk(p)
tsk(pp)
Pulse Skew
Part-to-Part Skew; NOTE 3, 4
fREF = 100MHz
10
fREF = 122.88MHz,
Square Wave, VPP = 0.8V,
Integration Range: 1kHz– 40MHz
90
fREF = 122.88MHz,
Square Wave, VPP = 0.8V, Integration
Range: 10kHz – 20MHz
60
fREF = 122.88MHz,
Square Wave, VPP = 0.8V, Integration
Range: 12kHz – 20MHz
55
fREF = 156.25MHz,
Square Wave, VPP = 1V, Integration
Range: 1kHz– 40MHz
61
Buffer Additive Phase Jitter,
fREF = 156.25MHz,
tJIT RMS; refer to Additive Phase Square Wave, VPP = 1V, Integration
Jitter Section
Range: 10kHz – 20MHz
45
fREF = 156.25MHz,
Square Wave, VPP = 1V, Integration
Range: 12kHz – 20MHz
45
fREF = 156.25MHz
Square Wave, VPP = 0.5V, Integration
Range: 1kHz– 40MHz
60
fREF = 156.25MHz,
Square Wave, VPP = 0.5V, Integration
Range: 10kHz – 20MHz
45
fREF = 156.25MHz,
Square Wave, VPP = 0.5V, Integration
Range: 12kHz – 20MHz
45
tR / tF
VPP
Output Rise/ Fall Time
Differential Input Voltage;
NOTE 5, 7
20% to 80%
f < 1.5GHz
f > 1.5GHz
70 110
0.1
0.2
VCMR
Common Mode Input
Voltage; NOTE 5, 6, 7
1.0
VO(pp)
VDIFF_OUT
Output Voltage Swing,
Peak-to-Peak
Differential Output Voltage
Swing, Peak-to-Peak
VCC = 3.3V ± 5%, fREF 2GHz
VCC = 2.5V ± 5%, fREF 2GHz
VCC = 3.3V ± 5%, fREF 2GHz
VCC = 2.5V ± 5%, fREF 2GHz
0.45 0.68
0.45 0.68
0.9 1.36
0.9 1.36
NOTES on next page.
Maximum Units
2 GHz
V/ns
550 ps
dB
33 ps
50 ps
150 ps
fs
fs
fs
76 fs
60 fs
60 fs
90 fs
80 fs
80 fs
170
1.5
1.5
VCC – 0.3
0.90
0.90
1.8
1.8
ps
V
V
V
V
V
V
V
IDT8SLVP1212ANLGI REVISION A JANUARY 28, 2014
5
©2014 Integrated Device Technology, Inc.
5 Page 
IDT8SLVP1212I Data Sheet
LOW PHASE NOISE, 1-TO-12, 3.3V, 2.5V LVPECL OUTPUT FANOUT BUFFER
Applications Information
Wiring the Differential Input to Accept Single-Ended Levels
The IDT8SLVP1212I inputs can be interfaced to LVPECL, LVDS,
CML or LVCMOS drivers. Figure 1A illustrates how to dc couple a
single LVCMOS input to the IDT8SLVP1212I. The value of the series
resistance RS is calculated as the difference between the
transmission line impedance and the driver output impedance. This
resistor should be placed close to the LVCMOS driver. To avoid
cross-coupling of single-ended LVCMOS signals, apply the LVCMOS
signals to no more than one PCLK input.
A practical method to implement Vth is shown in Figure 1B below.
The reference voltage Vth = V1 = VCC/2, is generated by the bias
resistors R1 and R2. The bypass capacitor (C1) is used to help filter
noise on the DC bias. This bias circuit should be located as close to
the input pin as possible.
The ratio of R1 and R2 might need to be adjusted to position the V1
in the center of the input voltage swing. For example, if the input clock
swing is 2.5V and VCC = 3.3V, R1 and R2 value should be adjusted
to set V1 at 1.25V. The values below apply when both the
single-ended swing and VCC are at the same voltage.
Figure 1A. DC-Coupling a Single LVCMOS Input to the
IDT8SLVP1212I
When using single-ended signaling, the noise rejection benefits of
differential signaling are reduced. Even though the differential input
can handle full rail LVCMOS signaling, it is recommended that the
amplitude be reduced, particularly if both input references are
LVCMOS to minimize cross talk. The datasheet specifies a lower
differential amplitude, however this only applies to differential signals.
For single-ended applications, the swing can be larger, however VIL
cannot be less than -0.3V and VIH cannot be more than VCC + 0.3V.
Figure 1B shows a way to attenuate the PCLK input level by a factor
of two as well as matching the transmission line between the
LVCMOS driver and the IDT8SLVP1212I at both the source and the
load. This configuration requires that the sum of the output
impedance of the driver (Ro) and the series resistance (Rs) equals
the transmission line impedance. R3 and R4 in parallel should equal
the transmission line impedance; for most 50 applications, R3 and
R4 will be 100. The values of the resistors can be increased to
reduce the loading for slower and weaker LVCMOS driver.
Though some of the recommended components of Figure 1B might
not be used, the pads should be placed in the layout so that they can
be utilized for debugging purposes. The datasheet specifications are
characterized and guaranteed by using a differential signal.
Figure 1B. Alternative DC Coupling a Single LVCMOS Input to the IDT8SLVP1212I
IDT8SLVP1212ANLGI REVISION A JANUARY 28, 2014
11
©2014 Integrated Device Technology, Inc.
11 Page | ||
| Páginas | Total 25 Páginas | |
| PDF Descargar | [ Datasheet IDT8SLVP1212I.PDF ] | |
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