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PDF 8SLVP2104 Data sheet ( Hoja de datos )
| Número de pieza | 8SLVP2104 | |
| Descripción | LVPECL Output Fanout Buffer | |
| Fabricantes | IDT | |
| Logotipo |  |
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Low Phase Noise, Dual 1-to-4, 3.3V, 2.5V
LVPECL Output Fanout Buffer
8SLVP2104
DATA SHEET
General Description
The 8SLVP2104I is a high-performance differential dual LVPECL
fanout buffer. The device is designed for the fanout of high-frequency,
very low additive phase-noise clock and data signals. The
8SLVP2104I is characterized to operate from a 3.3V or 2.5V power
supply. Guaranteed output-to-output and part-to-part skew
characteristics make the 8SLVP2104I ideal for those clock
distribution applications demanding well-defined performance and
repeatability. Two selectable differential inputs and four low skew
outputs are available. The integrated bias voltage reference enable
easy interfacing of single-ended signals to the device inputs. The
device is optimized for low power consumption and low additive
phase noise.
Features
• Two 1:4, low skew, low additive jitter LVPECL output pairs
• Two differential clock input pairs
• Differential pairs can accept the following differential input
levels: LVDS, LVPECL, CML
• Maximum input clock frequency: 2GHz
• Output skew: 8ps (typical)
• Propagation delay: 270ps (maximum)
• Low additive phase jitter, RMS: 47fs (maximum)
• Full 3.3V and 2.5V supply voltage
• Maximum device current consumption (IEE): 93mA (maximum)
• Available in lead-free (RoHS 6), 28-Lead VFQFN package
• -40°C to 85°C ambient operating temperature
• Supports case temperature 105°C operations
• Differential PCLKA, nPCLKA and PCLKB, nPCLKB pairs can also
accept single-ended LVCMOS levels. See Applications section
Wiring the Differential Input Levels to Accept Single-ended Levels
(Figure 1A and Figure 1B).
Block Diagram
PCLKA
nPCLKA
VCC
VREFA
Voltage
Reference
PCLKB
nPCLKB
VCC
VREFB
Voltage
Reference
QA0
nQA0
QA1
nQA1
QA2
nQA2
QA3
nQA3
QB0
nQB0
QB1
nQB1
QB2
nQB2
QB3
nQB3
Pin Assignment
21 20 19 18 17 16 15
QB0 22
14 VEE
nQB0 23
13 nQA0
QB1 24
12 QA0
nQB1 25
11 VREFA
QB2 26
10 nPCLKA
nQB2 27
9 PCLKA
VCC 28
8 VCC
1 23 45 67
8SLVP2104I
28-Lead VFQFN
5mm x 5mm x 0.75mm package body
NB Package
Top View
8SLVP2104 REVISION C 6/8/15
1 ©2015 Integrated Device Technology, Inc.
1 page  
8SLVP2104 DATA SHEET
AC Electrical Characteristics
Table 4A. AC Electrical Characteristics, VCC = 3.3V ± 5% or 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
PCLKA,
fREF
Input
nPCLKA;
Frequency PCLKB,
nPCLKB
V/t
Input
Edge Rate
PCLKA,
nPCLKA;
PCLKB,
nPCLKB
1.5
tPD
Propagation Delay; NOTE
1
Channel_ISOL Channel Isolation
tsk(o)
Output Skew; NOTE 2, 3
PCLKA, nPCLKA to any
QAx, nQAx or PCLKB, nPCLKB to any
QBx, nQBx for VPP = 0.1V or 0.3V
fREF = 122.88MHz
Any Output
50
165
78
8
tsk(b)
Bank Skew; NOTE 3, 4
Within QAx, QBx
7
tsk(p)
tsk(pp)
Pulse Skew
Part-to-Part Skew; NOTE
3, 5
fREF = 100MHz
7
100
tJIT, SP
tR / tF
VPP
VCMR
Spurious Suppression,
Coupling from QA3 to QB0
Output Rise/ Fall Time
Peak-to-Peak Input
Voltage; NOTE 6, 8
Common Mode Input
Voltage; NOTE 6, 7, 8
fQB0 = 500MHz, VPP(PCLKB) = 0.15V,
VCMR(PCLKB) = 1V and
fQA3 = 62.5MHz, VPP(PCLKA) = 1V,
VCMR(PCLKA) = 1V
fQB0 = 500MHz, VPP(PCLKB) = 0.15V,
VCMR(PCLKB) = 1V and
fQA3 = 15.625MHz, VPP(PCLKA) = 1V,
VCMR(PCLKA) = 1V
20% to 80%
fREF < 1.5 GHz
fREF > 1.5 GHz
40
0.1
0.2
1.0
-66
-77
100
VO(pp)
VDIFF_OUT
Output Voltage Swing,
Peak-to-Peak
Differential Output Voltage
Swing, (Peak-to-Peak)
VCC = 3.3V, fREF 2GHz
VCC = 2.5V, fREF 2GHz
VCC = 3.3V, fREF 2GHz
VCC = 2.5V, fREF 2GHz
0.4 0.6
0.35 0.55
0.8 1.2
0.7 1.1
Maximum
2
270
25
20
27
200
150
1.5
1.5
VCC – 0.6
1.0
1.0
2.0
2.0
Units
GHz
V/ns
ps
dB
ps
ps
ps
ps
dB
dB
ps
V
V
V
V
V
V
V
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Measured from the differential input crossing point to the differential output crosspoint.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential
crosspoints.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Defined as skew within a bank with equal load conditions. Measured at the differential crosspoints.
NOTE 5: Defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and
with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential crosspoints.
NOTE 6: VIL should not be less than -0.3V. VIH should not be higher than VCC.
NOTE 7: Common mode input voltage is defined as the crosspoint.
NOTE 8: For single-ended LVCMOS input applications, please refer to the Applications Information, Wiring the Differential Input to accept
single-ended levels, Figures 1A and 1B.
REVISION C 6/8/15
5 LOW PHASE NOISE, DUAL 1-TO-4, 3.3V, 2.5V LVPECL OUTPUT
FANOUT BUFFER
5 Page 
8SLVP2104 DATA SHEET
Recommendations for Unused Input and Output Pins
Inputs:
PCLKx/nPCLKx Inputs
For applications requiring only one differential input, the unused
PCLKx and nPCLKx pins can be left floating. Though not required,
but for additional protection, a 1k resistor can be tied from the
unused PCLKx input to ground.
Outputs:
LVPECL Outputs
All unused LVPECL outputs can be left floating. We recommend that
there is no trace attached. Both sides of the differential output pair
should either be left floating or terminated.
VREFX
Unused VREFA and VREFB pins can be left floating. We recommend
that there is no trace attached.
REVISION C 6/8/15
11 LOW PHASE NOISE, DUAL 1-TO-4, 3.3V, 2.5V LVPECL OUTPUT
FANOUT BUFFER
11 Page | ||
| Páginas | Total 23 Páginas | |
| PDF Descargar | [ Datasheet 8SLVP2104.PDF ] | |
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