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PDF 8SLVP1204 Data sheet ( Hoja de datos )

Número de pieza 8SLVP1204
Descripción LVPECL Output Fanout Buffer
Fabricantes IDT 
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Low Phase Noise, 2:4, 3.3V, 2.5V
LVPECL Output Fanout Buffer
8SLVP1204
DATA SHEET
General Description
The 8SLVP1204 is a high-performance differential LVPECL fanout
buffer. The device is designed for the fanout of high-frequency, very
low additive phase-noise clock and data signals. The 8SLVP1204 is
characterized to operate from a 3.3V or 2.5V power supply.
Guaranteed output-to-output and part-to-part skew characteristics
make the 8SLVP1204 ideal for those clock distribution applications
demanding well-defined performance and repeatability. Two
selectable differential inputs and four low skew outputs are available.
The integrated bias voltage reference enables easy interfacing of
single-ended signals to the device inputs. The device is optimized for
low power consumption and low additive phase noise.
Features
Four low skew, low additive jitter LVPECL output pairs
Two selectable, differential clock input pairs
Differential PCLKx pairs can accept the following differential input
levels: LVDS, LVPECL, CML
Differential PCLKx pairs can also accept single-ended LVCMOS
levels. See Section, “Applications Information”, section, “Wiring
the Differential Input to Accept Single-Ended Levels” (Figures 1A
and 1B)
Maximum input clock frequency: 2GHz
LVCMOS interface levels for the control input, (input select)
Output skew: 5ps (typical), at 3.63V
Propagation delay: 200ps (typical), at 3.63V
Low additive phase jitter, RMS; fREF = 156.25MHz, VPP = 1V,
12kHz - 20MHz: 40fs (maximum), at 3.63V
Maximum device current consumption (IEE): 60mA (maximum),
at 3.63V
Full 3.3V±5%, 3.3V±10% or 2.5V±5% supply
Lead-free (RoHS 6), 16-Lead VFQFN packaging
-40°C to 85°C ambient operating temperature
Supports case temperature 105°C operations
Block Diagram
VCC
PCLK0 Pulldown
nPCLK0 Pullup/Pulldown
VCC
PCLK1 Pulldown
nPCLK1 Pullup/Pulldown
0 fREF
1
SEL Pulldown
VREF
Voltage
Reference
Pin Assignment
16 15 14 13
Q0
VEE 1
12 nQ1
nQ0
SEL 2
11 Q1
Q1
PCLK1 3
10 nQ0
nQ1 nPCLK1 4
9 Q0
5 6 78
Q2
nQ2
Q3
nQ3 8SLVP1204
16-Lead, 3mm x 3mm VFQFN Package
8SLVP1204 REVISION D 6/8/15
1 ©2015 Integrated Device Technology, Inc.

1 page




8SLVP1204 pdf
8SLVP1204 DATA SHEET
Table 4F. LVPECL DC Characteristics, VCC = 3.3V ±10%, VEE = 0V, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
IIH
Input High Current
PCLK0, nPCLK0
PCLK1, nPCLK1
VCC = VIN = 3.63V
PCLK0, PCLK1
IIL
Input Low Current
nPCLK0, nPCLK1
VREF
Reference Voltage for Input Bias
VOH Output High Voltage1
VOL Output Low Voltage1
NOTE 1. Outputs terminated with 50to VCC – 2V.
VCC = 3.63V, VIN = 0V
VCC = 3.63V, VIN = 0V
IREF = ±1mA
-10
-150
VCC – 1.6
VCC – 1.1
VCC – 2.0
Typical
VCC – 1.3
VCC – 0.9
VCC – 1.65
Maximum
150
VCC – 1.1
VCC – 0.7
VCC – 1.5
Units
µA
µA
µA
V
V
V
Table 4G. LVPECL DC Characteristics, VCC = 3.3V ±5%, VEE = 0V, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
IIH
Input High Current
PCLK0, nPCLK0
PCLK1, nPCLK1
VCC = VIN = 3.465V
PCLK0, PCLK1
IIL Input Low Current
nPCLK0, nPCLK1
VREF
Reference Voltage for Input Bias
VOH Output High Voltage1
VOL Output Low Voltage1
NOTE 1. Outputs terminated with 50to VCC – 2V.
VCC = 3.465V, VIN = 0V
VCC = 3.465V, VIN = 0V
IREF = ±1mA
-10
-150
VCC – 1.6
VCC – 1.1
VCC – 2.0
Typical
VCC – 1.3
VCC – 0.9
VCC – 1.65
Maximum
150
VCC – 1.1
VCC – 0.7
VCC – 1.5
Units
µA
µA
µA
V
V
V
Table 4H. LVPECL DC Characteristics, VCC = 2.5V ±5%, VEE = 0V, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
IIH
Input High Current
PCLK0, nPCLK0
PCLK1, nPCLK1
VCC = VIN = 2.625V
PCLK0, PCLK1
IIL Input Low Current
nPCLK0, nPCLK1
VREF
Reference Voltage for Input Bias
VOH Output High Voltage1
VOL Output Low Voltage1
NOTE 1. Outputs terminated with 50to VCC – 2V.
VCC = 2.625V, VIN = 0V
VCC = 2.625V, VIN = 0V
IREF = ±1mA
-10
-150
VCC – 1.6
VCC – 1.1
VCC – 2.0
Typical
VCC – 1.3
VCC – 0.9
VCC – 1.6
Maximum
150
VCC – 1.1
VCC – 0.7
VCC – 1.5
Units
µA
µA
µA
V
V
V
REVISION D 6/8/15
5 LOW PHASE NOISE, 2:4, 3.3V, 2.5V LVPECL OUTPUT
FANOUT BUFFER

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8SLVP1204 arduino
8SLVP1204 DATA SHEET
Parameter Measurement Information, continued
nPCLK0
PCLK0
nPCLK1
PCLK1
nQ[0:3]
Q[0:3]
Input Skew
tPD2
tPD1
tsk(i)
tsk(i) = |tPD1 - tPD2|
Spectrum of Output Signal Q
A0 MUX selects active
input clock signal
MUX_ISOLATION = A0 – A1
A1 MUX selects other input
MUX Isolation
ƒ
(fundamental)
Frequency
nQx
Qx
nQy
Qy
Output Skew
nPCLK[0:1]
PCLK[0:1]
nQ[0:3]
Q[0:3]
tPD
Propagation Delay
nQ[0:3]
20%
Q[0:3]
80%
tR
Output Rise/Fall Time
REVISION D 6/8/15
80%
tF
VO(PP)
20%
11
LOW PHASE NOISE, 2:4, 3.3V, 2.5V LVPECL OUTPUT
FANOUT BUFFER

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