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PDF ICS8S89832I Data sheet ( Hoja de datos )

Número de pieza ICS8S89832I
Descripción 1-to-4 Differential-to-LVDS Fanout Buffer
Fabricantes IDT 
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Low Skew, 1-to-4 Differential-to-LVDS
Fanout Buffer
ICS8S89832I
DATA SHEET
General Description
The ICS8S89832I is a high speed 1-to-4
ICS Differential-to-LVDS Fanout Buffer. The ICS8S89832I
HiPerClockS™ is optimized for high speed and very low output skew,
making it suitable for use in demanding applications
such as SONET, 1 Gigabit and 10 Gigabit Ethernet,
and Fibre Channel. The internally terminated differential input and
VREF_AC pin allow other differential signal families such as LVPECL,
LVDS, and SSTL to be easily interfaced to the input with minimal use
of external components. The device also has an output enable pin
which may be useful for system test and debug purposes. The
ICS8S89832I is packaged in a small 3mm x 3mm 16-pin VFQFN
package which makes it ideal for use in space-constrained
applications.
Features
Four differential LVDS output pairs
IN, nIN input pairs can accept the following differential input levels:
LVPECL, LVDS, SSTL
50internal input termination to VT
Maximum output frequency: 2GHz
Output skew: 25ps (maximum)
Part-to-part skew: 200ps (maximum)
Propagation delay: 550ps (maximum)
Additive phase jitter, RMS: 0.09ps (typical)
Full 2.5V supply mode
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Block Diagram
IN
50
VT
50
nIN
VREF_AC
EN
DQ
CLK
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Pin Assignment
16 15 14 13
Q1 1
12 IN
nQ1 2
11 VT
Q2 3
10 VREF_AC
nQ2 4
9 nIN
5 6 78
ICS8S89832I
16-Lead VFQFN
3mm x 3mm x 0.925mm package body
K Package
Top View
ICS8S89832AKI REVISION A JANUARY 11, 2010
1
©2010 Integrated Device Technology, Inc.

1 page




ICS8S89832I pdf
ICS8S89832I Data Sheet
LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
Table 4C. Differential DC Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
RIN
VIH
VIL
VIN
VDIFF_IN
IIN
VREF_AC
Differential Input Resistance IN, nIN
Input High Voltage
IN, nIN
Input Low Voltage
IN, nIN
Input Voltage Swing; NOTE 1
Differential Input Voltage Swing
Input Current; NOTE 2
IN, nIN
Reference Voltage
IN to VT, nIN to VT
40
1.2
0
0.15
0.3
VDD – 1.40
NOTE 1: VIL should not be less than -0.3V.
NOTE 2: Guaranteed by design.
Typical
50
VDD – 1.35
Maximum
60
VDD
VIH – 0.15
1.2
35
VDD – 1.30
Units
V
V
V
V
mA
V
Table 4D. LVDS DC Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
VOD
VOD
VOS
VOS
Differential Output Voltage
VOD Magnitude Change
Offset Voltage
VOS Magnitude Change
.
Minimum
247
1.125
Typical
Maximum
454
50
1.375
50
Units
mV
mV
V
mV
AC Electrical Characteristics
Table 5. AC Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
fOUT
tPD
Operating Frequency
Propagation Delay; (Differential)
NOTE 1
tsk(o) Output Skew; NOTE 2, 3
tsk(pp) Part-to-Part Skew; NOTE 3, 4
tjit
Buffer Additive Phase Jitter, RMS; refer to
Additive Phase Jitter Section
200MHz, Integration Range:
12kHz - 20MHz
ts /tH
tR / tF
Clock Enable Setup Time EN to IN, nIN
Output Rise/Fall Time
20% to 80%
Minimum
300
300
50
Typical
0.09
Maximum
2
550
25
200
235
Units
GHz
ps
ps
ps
ps
ps
ps
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device
is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal
equilibrium has been reached under these conditions.
All parameters are measured at 1.5GHz unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency and
with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
ICS8S89832AKI REVISION A JANUARY 11, 2010
5
©2010 Integrated Device Technology, Inc.

5 Page





ICS8S89832I arduino
ICS8S89832I Data Sheet
LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS8S89832I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8S89832I is the sum of the core power plus the analog power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 2.5V + 5% = 2.625V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
• Power (core)MAX = VDD_MAX * IDD_MAX = 2.625V * 95mA = 249.375mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 74.7°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.249W * 74.7°C/W = 103.6°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 6. Thermal Resistance θJA for 16 Lead VFQFN Forced Convection
θJA by Velocity
Meters per Second
0
Multi-Layer PCB, JEDEC Standard Test Boards
74.7°C/W
1
65.3°C/W
2.5
58.5°C/W
ICS8S89832AKI REVISION A JANUARY 11, 2010
11
©2010 Integrated Device Technology, Inc.

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