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PDF 8P73S674 Data sheet ( Hoja de datos )

Número de pieza 8P73S674
Descripción 1.8V LVPECL Clock Divider
Fabricantes IDT 
Logotipo IDT Logotipo



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1.8V LVPECL Clock Divider
8P73S674
DATA SHEET
General Description
The 8P73S674 is a 1.8V LVPECL Clock Divider and Fanout Buffer.
The device has been designed for clock signal division and fanout in
wireless base station (radio and base band), high-end computing and
telecommunication equipment. The device is optimized to deliver
excellent phase noise performance. The 8P73S674 uses SiGe
technology for an optimum of high clock frequency and low phase
noise performance, combined with high power supply noise rejection.
The device offers the frequency division by ÷1, ÷2, ÷4 and ÷8. Four
low-skew 1.8V LVPECL outputs are available for and support clock
output frequencies up to 1GHz (÷1 frequency division). 1.8V LVPECL
outputs are terminated 50to GND. Outputs can be disabled to save
power consumption if not used. The device is packaged in a lead-free
(RoHS 6) 20-lead VFQFN package. The extended temperature range
supports wireless infrastructure, telecommunication and networking
end equipment requirements. The device is a member of the
high-performance clock family from IDT.
Features
Clock signal division and distribution
SiGe technology for high-frequency and fast signal rise/fall times
Four low-skew LVPECL clock outputs
Supports frequency division of ÷1, ÷2, ÷4 and ÷8
Maximum Output frequency: 1GHz
Output skew: 100ps (maximum)
LVPECL output rise/fall time (20% - 80%): 220ps (maximum)
1.8V core and output supply mode
Supports 1.8V I/O LVCMOS logic levels for all control pins
-40°C to +85°C ambient operating temperature
Lead-free (RoHS 6) 20-lead VFQFN packaging
Block Diagram
IN
nIN
VT
N[1:0]
nOEA
nOEB
2x 50
÷N
8P73S674 REVISION 1 12/17/14
Pin Assignment
Q0
nQ0
 
20 19 18 17 16
nIN 1
Q1
nQ1 NC 2
15 nQ1
14 Q1
Q2
VT 3
8P73S674
13 nQ2
nQ2
IN 4
12 Q2
Q3
nQ3
N0 5
11 VCC
6 7 8 9 10
20-pin, 2.15mm x 2.15mm, EPad, VFQFN Package
1 ©2014 Integrated Device Technology, Inc.

1 page




8P73S674 pdf
8P73S674 DATA SHEET
Table 4D. LVPECL DC Characteristics, VCC = 1.8V ±0.15V, TA = -40°C to +85°C
Symbol
VOH
VOL
VSWING
Parameter
Output High Voltage1
Output Low Voltage1
Peak-to-Peak Output
Voltage Swing1
Test Conditions
Minimum
VCC – 1.1
0.6
NOTE 1: Outputs terminated with 50to GND.
Typical
Maximum
VCC – 0.75
VCC – 1.5
1.0
Units
V
V
V
AC Electrical Characteristics
Table 5. AC Characteristics, VCC = 1.8V ±0.15V, TA = -40°C to +85°C1, 2
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
VPP
VDIFF_IN
Input Voltage Swing
Differential Input
Voltage Swing
IN, nIN
IN, nIN
0.2 1 V
0.4 2 V
VCMR
Common Mode Input
Voltage3
IN, nIN
0.9
VCC –VPP/2
V
N = ÷1
1000
MHz
fOUT
Output Frequency, Q[3:0]
N = ÷2
N = ÷4
500 MHz
250 MHz
N = ÷8
125 MHz
fIN
tsk(o)
Input Frequency, IN, nIN
Output Skew4, 5
1000
MHz
40 100 ps
tPD
tsk(pp)
Propagation Delay
Part-to-Part Skew4, 6
N = ÷1
N = ÷2, ÷4, ÷8
200
400
600 ps
900 ps
500 ps
tR / tF
Output
Rise/Fall Time
10%-90%
20%-80%
270 410 ps
150 220 ps
tjit(Ø)
Phase Jitter Noise Floor, >100kHz
offset7
any Q, fOUT = 1000MHz
-153
dBc/Hz
tjit(Ø) Additive Phase Noise, RMS
122.88 MHz; 1kHz-40MHz
122.88 MHz; 12kHz-20MHz
100 180 fs
60 120 fs
odc Output Duty Cycle
50% Input Duty Cycle 45 50 55 %
NOTE 1: Outputs terminated with 50to GND.
NOTE 2: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the
device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after
thermal equilibrium has been reached under these conditions.
NOTE 3: Common mode input voltage is defined as the signal crosspoint.
NOTE 4: This parameter is defined in accordance with JEDEC standard 65.
NOTE 5: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential
crosspoints.
NOTE 6: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the output differential
crosspoints.
NOTE 7: VCMR is set to 1.12V.
REVISION 1 12/17/14
5 1.8V LVPECL CLOCK DIVIDER

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8P73S674 arduino
Reliability Information
Table 7. JA vs. Air Flow Table for a 20-Lead VFQFN
Meters per Second
JA at 0 Air Flow
0
Multi-Layer PCB, JEDEC Standard Test Boards
70.7°C/W
Transistor Count
The transistor count for the 8P73S674 is: 1,238
8P73S674 DATA SHEET
1
67.0°C/W
2
65.3°C/W
REVISION 1 12/17/14
11 1.8V LVPECL CLOCK DIVIDER

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