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PDF S70GL02GT Data sheet ( Hoja de datos )
| Número de pieza | S70GL02GT | |
| Descripción | 2-Gbit (256-Mbyte) 3.0V Flash Memory | |
| Fabricantes | Cypress Semiconductor | |
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S70GL02GT
2-Gbit (256-Mbyte)
3.0V Flash Memory
General Description
The Cypress S70GL02GT 2-Gigabit MirrorBit® Flash memory device is fabricated on 45-nm MirrorBit® Eclipse™ process technology.
This device offers a fast page access time of 25 ns with a corresponding random access time of 110 ns. It features a Write Buffer
that allows a maximum of 256 words/512 bytes to be programmed in one operation, resulting in faster effective programming time
than standard single byte/word programming algorithms. This makes the device an ideal product for today’s embedded applications
that require higher density, better performance and lower power consumption.
This document contains information for the S70GL02GT device, which is a dual-die stack of two S29GL01GT die. For detailed
specifications, please refer to the discrete die data sheet:
Document
S29GL01GT, S29GL512T Data Sheet
Cypress Document Number
002-00247
Distinctive Characteristics
CMOS 3.0 Volt Core with Versatile I/O™
Two 1024 Megabit (S29GL01GT) in a single 64-ball Fortified-
BGA package (see S29GL01GT datasheet for full
specifications)
45 nm MirrorBit Eclipse process technology
Single supply (VCC) for read / program / erase (2.7V to 3.6V)
Versatile I/O Feature
– Wide I/O voltage (VIO): 1.65V to VCC
x8 and x16 data bus
16-word/32-byte page read buffer
512-byte Programming Buffer
– Programming in Page multiples, up to a maximum of
512 bytes
Sector Erase
– Uniform 128-kbytes sectors
– S70GL02GT: two thousand forty-eight sectors
Suspend and Resume commands for Program and Erase
operations
Status Register, Data Polling, and Ready/Busy pin methods
to determine device status
Advanced Sector Protection (ASP)
– Volatile and non-volatile protection methods for each
sector
Separate 1024-bye One Time Program (OTP) array with two
lockable regions
– Available in each device Support for CFI (Common Flash
Interface)
WP# input
– Protects the last sector of the device, regardless of sector
protection settings
Temperature Range / Grade
– Industrial (–40°C to +85°C)
– Industrial Plus (–40°C to +105°C)
– Automotive, AEC-Q100 Grade 3 (-40°C to +85°C)
– Automotive, AEC-Q100 Grade 2 (-40°C to +105°C)
100,000 Program-Erase cycles
20-year data retention
Packaging Options
– 64-ball LSH Fortified BGA, 13 mm x 11 mm
Performance Characteristics
Max. Read Access Times (ns) (Note 1)
Parameter
Random Access Time (tACC)
Page Access Time (tPACC)
CE# Access Time (tCE)
OE# Access Time (tOE)
110
20
110
25
Notes
1. Access times are dependent on VIO operating ranges. See Ordering Information on page 4 for further details.
2. Contact a sales representative for availability.
2 Gb
120
30
120
35
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 002-13915 Rev. *A
• San Jose, CA 95134-1709 • 408-943-2600
Revised October 21, 2016
1 page  
S70GL02GT
2. Input/Output Descriptions and Logic Symbol
Table 2.1 identifies the input and output package connections provided on the device.
Table 2.1 Input/Output Descriptions
Symbol
DQ14–DQ0
DQ15/A-1
CE#
OE#
WE#
A26-A0
VCC
VIO
VSS
RY/BY#
BYTE#
RESET#
WP#
NC
DNU
RFU
Type
Description
I/O Data inputs and outputs.
DQ15: Data inputs and outputs.
Input/Output
A-1: LSB address input in byte mode.
Input
Input
Chip Enable. At VIL, selects the device for data transfer with the host memory controller.
Output Enable. At VIL, causes outputs to be actively driven. At VIH, causes outputs to be high
impedance (High-Z).
Input
Write Enable. At VIL, indicates data transfer from host to device. At VIH, indicates data transfer
is from device to host.
Input
Address lines for S29GL02GT.
Supply
Core power supply.
Supply
Versatile IO power supply.
Supply
Power supplies ground.
Output — open
drain
Ready/Busy. Indicates whether an Embedded Algorithm is in progress or complete. At VIL, the
device is actively engaged in an Embedded Algorithm such as erasing or programming. At
High-Z, the device is ready for read or a new command write — requires external pull-up
resistor to detect the High-Z state. Multiple devices may have their
RY/BY# outputs tied together to detect when all devices are ready.
Input
Selects data bus width. At VIL, the device is in byte configuration and data I/O pins DQ7-DQ0
are active and DQ15/A-1 becomes the LSB address input. At VIH, the device is in word
configuration and data I/O pins DQ15-DQ0 are active.
Input
Hardware Reset. At VIL, causes the device to reset control logic to its standby state, ready for
reading array data.
Input
No Connect
Write Protect. At VIL, disables program and erase functions in the highest address 64-kword
(128-kB) sector of the device. At VIH, the sector is not protected. WP# has an internal pull up;
When unconnected WP# is at VIH.
Not Connected internally. The pin/ball location may be used in Printed Circuit Board (PCB) as
part of a routing channel.
Reserved
Do Not Use. Reserved for use by Cypress. The pin/ball is connected internally. The input has
an internal pull down resistance to VSS. The pin/ball can be left open or tied to VSS on the
PCB.
No Connect
Reserved for Future Use. Not currently connected internally but the pin/ball location should be
left unconnected and unused by PCB routing channel for future compatibility. The pin/ball may
be used by a signal in the future.
Document Number: 002-13915 Rev. *A
Page 5 of 20
5 Page 
S70GL02GT
Table 6.2 DC Characteristics (–40°C to +105°C)
Parameter
Description
Test Conditions
Min
Typ
(Note 2)
Max Unit
ILI Input Load Current
VIN = VSS to VCC, VCC = VCC max
All
Others
WP#,
BYTE#
±0.04
±0.5
±2.0
µA
±2.0
ILO
ICC4
ICC5
ICC6
ICC7
Output Leakage Current
VCC Standby Current
VCC Reset Current (Notes 2, 7)
Automatic Sleep Mode (3)
VCC Current during power up
(Notes 2, 6)
VOUT = VSS to VCC, VCC = VCC max
CE#, RESET#, OE# = VIH, VIH = VIO
VIL = VSS, VCC = VCC max
CE# = VIH, RESET# = VIL,
VCC = VCC max
VIH = VIO, VIL = VSS,
VCC = VCC max, tACC + 30 ns
VIH = VIO, VIL = VSS,
VCC = VCC max, tASSB
RESET# = VIO, CE# = VIO, OE# =
VIO, VCC = VCC max,
±0.04
140
±2.0 µA
400 µA
20 40 mA
6 12 mA
200 400 µA
106 160 mA
Notes
1. ICC active while Embedded Algorithm is in progress.
2. Not 100% tested.
3. Automatic sleep mode enables the lower power mode when addresses remain stable for a designated time.
4. VIO = 1.65V to VCC or 2.7V to VCC depending on the model.
5. VCC = 3V and VIO = 3V or 1.8V. When VIO is at 1.8V, I/O pins cannot operate at >1.8V.
6. During power-up there are spikes of current demand, the system needs to be able to supply this current to insure the part initializes correctly.
7. If an embedded operation is in progress at the start of reset, the current consumption will remain at the embedded operation specification until the embedded operation
is stopped by the reset. If no embedded operation is in progress when reset is started, or following the stopping of an embedded operation, ICC7 will be drawn during
the remainder of tRPH. After the end of tRPH the device will go to standby mode until the next read or write.
8. For all other DC current values please refer to the S29GL01GT/S29GL512T data sheet.
Document Number: 002-13915 Rev. *A
Page 11 of 20
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| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet S70GL02GT.PDF ] | |
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