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PDF S6E2C59J0A Data sheet ( Hoja de datos )

Número de pieza S6E2C59J0A
Descripción Microcontroller
Fabricantes Cypress Semiconductor 
Logotipo Cypress Semiconductor Logotipo



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No Preview Available ! S6E2C59J0A Hoja de datos, Descripción, Manual

S6E2C5 Series
32-bit ARM® Cortex®-M4F
FM4 Microcontroller
Devices in the S6E2C5 Series are highly integrated 32-bit microcontrollers with high performance and competitive cost. This
series is based on the ARM Cortex-M4F processor with on-chip flash memory and SRAM. The series has peripherals such as
motor control timers, A/D converters, and communications interfaces (USB, CAN, UART, CSIO (SPI), I2C, LIN). The products that
are described in this data sheet are placed into TYPE3-M4 product categories "FM4 Family Peripheral Manual Main Part
(002-04856)."
Features
32-bit ARM Cortex-M4F Core
Processor version: r0p1
Up to 200 MHz frequency operation
FPU built-in
Support DSP instructions
Memory protection unit (MPU): improves the reliability of an
embedded system
Integrated nested vectored interrupt controller (NVIC): 1 NMI
(non-maskable interrupt) and 128 peripheral interrupts and
16 priority levels
24-bit system timer (Sys Tick): system timer for OS task
management
On-chip Memories
Flash memory
This series is based on two independent on-chip flash
memories.
Up to 2048 Kbytes
Built-in flash accelerator system with 16 Kbytes trace buffer
memory
Read access to flash memory that can be achieved without
wait-cycle up to an operating frequency of 72 MHz. Even at
the operating frequency more than 72 MHz, an equivalent
single cycle access to flash memory can be obtained by
the flash accelerator system.
Security function for code protection
SRAM
This is composed of three independent SRAMs (SRAM0,
SRAM1 and SRAM2). SRAM0 is connected to the I-code bus
or D-code bus of Cortex-M4F core. SRAM1 and SRAM2 are
connected to system bus of Cortex-M4F core.
SRAM0: up to 192 Kbytes
SRAM1: 32 Kbytes
SRAM2: 32 Kbytes
External Bus Interface
Supports SRAM, NOR, NAND flash and SDRAM device
Up to 9 chip selects CS0 to CS8 (CS8 is only for SDRAM)
8-/16-/32-bit data width
Up to 25-bit address bus
Supports address/data multiplexing
Supports external RDY function
Supports scramble function
Possible to set the validity/invalidity of the scramble function
for the external areas 0x6000_0000 to 0xDFFF_FFFF in 4
Mbytes units.
Possible to set two kinds of the scramble key
Note: It is necessary to use the Cypress provided software
library to use the scramble function.
USB Interface (Max two Channels)
The USB interface is composed of a function and a host.
USB function
USB 2.0 Full-speed supported
Max 6 EndPoint supported
EndPoint 0 is control transfer
EndPoint 1, 2 can be selected bulk-transfer,
interrupt-transfer or isochronous-transfer
EndPoint 3 to 5 can select bulk-transfer or
interrupt-transfer
EndPoint 1 to 5 comprise double buffer
The size of each endpoint is as follows.
Endpoint 0, 2 to 5: 64 byte
EndPoint 1: 256 byte
USB host
USB2.0 Full-Speed/Low-Speed supported
Bulk-transfer, interrupt-transfer, and isochronous-transfer
support
USB Device connected/dis-connected automatically detect
IN/OUT token handshake packet automatically
Max 256-byte packet length supported
Wake-up function supported
Cypress Semiconductor Corporation
Document Number: 002-04984 Rev.*A
• 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Revised February 8, 2016

1 page




S6E2C59J0A pdf
S6E2C5 Series
Low-power Consumption Mode
Six low power consumption modes are supported.
Sleep
Timer
RTC
Stop
Deep standby RTC (selectable from with/without RAM
retention)
Deep standby stop (selectable from with/without RAM
retention)
Peripheral Clock Gating
The system can reduce the current consumption of the total
system with gating the operation clocks of peripheral
functions not used.
VBAT
The consumption power during the RTC operation can be
reduced by supplying the power supply independent from the
RTC (calendar circuit)/32 kHz oscillation circuit. The following
circuits can also be used.
RTC
32-kHz oscillation circuit
Power-on circuit
Back up register: 32 bytes
Port circuit
Debug
Serial wire JTAG debug port (SWJ-DP)
Embedded trace macrocells (ETM) provide comprehensive
debug and trace facilities.
AHB trace macrocells (HTM)
Unique ID
Unique value of the device (41-bit) is set.
Power Supply
Five power supplies
Wide range voltage:
VCC
= 2.7 V to 5.5 V
Power supply for USB ch 0 I/O:
USBVCC0 = 3.0 V to 3.6 V (when USB is used)
= 2.7 V to 5.5 V (when GPIO is used)
Power supply for USB ch 1 I/O:
USBVCC1 = 3.0 V to 3.6 V (when USB is used)
= 2.7 V to 5.5 V (when GPIO is used)
Power supply for VBAT:
VBAT
= 1.65 V to 5.5 V
Document Number: 002-04984 Rev.*A
Page 5 of 200

5 Page





S6E2C59J0A arduino
3. Pin Assignments
LQS144
(Top View)
S6E2C5 Series
VCC
PA0/RTO20_0/TIOA8_0/AIN2_0/INT00_0/MADATA00_0
PA1/RTO21_0/TIOA9_0/BIN2_0/MADATA01_0
PA2/RTO22_0/TIOA10_0/ZIN2_0/MADATA02_0
PA3/RTO23_0/TIOA11_0/MADATA03_0
PA4/RTO24_0/TIOA12_0/MADATA04_0
PA5/SIN1_0/RTO25_0/TIOA13_0/INT01_0/MADATA05_0
PA6/SOT1_0/DTTI2X_0/MADATA06_0
PA7/SCK1_0/IC20_0/MADATA07_0
PA8/SIN7_0/IC21_0/INT02_0/WKUP1/MADATA08_0
PA9/SOT7_0/IC22_0/MADATA09_0
PAA/SCK7_0/IC23_0/MADATA10_0
PAB/SCS70_0/RX0_0/FRCK2_0/INT03_0/MADATA11_0
PAC/SCS71_0/TX0_0/TIOB8_0/AIN3_0/MADATA12_0
PAD/SCK3_0/TIOB9_0/BIN3_0/MADATA13_0
PAE/ADTG_0/SOT3_0/TIOB10_0/ZIN3_0/MADATA14_0
PAF/SIN3_0/TIOB11_0/INT16_0/MADATA15_0
P08/SIN14_0/TIOB12_0/INT17_0/MDQM0_0
P09/SOT14_0/TIOB13_0/INT18_0/MDQM1_0
P0A/ADTG_1/SCK14_0/AIN2_1/MCLKOUT_0
P32/BIN2_1/INT19_0/S_DATA1_0
P33/FRCK0_0/ZIN2_1/S_DATA0_0
P34/IC03_0/INT00_1/S_CLK_0
VCC
VSS
P35/IC02_0/INT01_1/S_CMD_0
P36/IC01_0/INT02_1/S_DATA3_0
P37/IC00_0/INT03_1/S_DATA2_0
P38/ADTG_2/DTTI0X_0/S_WP_0
P39/SIN2_1/RTO00_0/TIOA0_1/AIN3_1/INT16_1/S_CD_0/MAD24_0
P3A/SOT2_1/RTO01_0/TIOA1_1/BIN3_1/INT17_1/MAD23_0
P3B/SCK2_1/RTO02_0/TIOA2_1/ZIN3_1/INT18_1/MAD22_0/MNALE_0
P3C/SIN13_0/RTO03_0/TIOA3_1/INT19_1/MAD21_0/MNCLE_0
P3D/SOT13_0/RTO04_0/TIOA4_1/MAD20_0/MNWEX_0
P3E/SCK13_0/RTO05_0/TIOA5_1/MAD19_0/MNREX_0
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
LQFP - 144
108 VSS
107 P83/UDP1
106 P82/UDM1
105 USBVCC1
104 P20/NMIX/WKUP0
103 P21/ADTG_4/SIN0_0/INT27_0/CROUT_0
102 P22/AN31/SOT0_0/INT26_0
101 P23/UHCONX1/AN30/SCK0_0/TIOB13_1
100 P24/AN29/TIOA13_1/MAD18_0
99 P25/AN28/RX1_0/INT25_0/MAD17_0
98 P26/TX1_0/MAD16_0
97 P27/AN27/SIN5_0/INT24_0/MAD15_0
96 P28/AN26/SOT5_0/MAD14_0
95 P29/AN25/SCK5_0/MAD13_0
94 P2A/AN24/CTS5_0/MAD12_0
93 P1F/AN15/RTS5_0/TIOB8_1/INT27_1/MAD11_0
92 P1E/AN14/TIOA8_1/INT26_1/MAD10_0
91 P1D/AN13/SCK12_0/TIOB5_2/TRACED3
90 P1C/AN12/SOT12_0/TIOA5_2/TRACED2
89 P1B/AN11/SIN12_0/TIOB4_2/INT11_0/TRACED1
88 P1A/AN10/SCK2_0/TIOA4_2/TRACED0
87 P19/AN09/SOT2_0/TIOB3_2/INT24_1/TRACECLK
86 P18/AN08/SIN2_0/TIOA3_2/INT10_0
85 P17/AN07/SCK11_0/TIOB2_2/ZIN1_2
84 P16/AN06/SOT11_0/TIOA2_2/BIN1_2
83 P15/AN05/SIN11_0/TIOB1_2/AIN1_2/INT09_0
82 P14/AN04/SOT6_1/TX1_1
81 P13/AN03/SIN6_1/RX1_1/INT25_1
80 P12/AN02/SCK10_0/TIOA1_2/ZIN0_2
79 P11/AN01/SOT10_0/TIOB0_2/BIN0_2
78 P10/AN00/SIN10_0/TIOA0_2/AIN0_2/INT08_0
77 AVRH
76 AVRL
75 AVSS
74 AVCC
73 VCC
Note:
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number.
For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
Document Number: 002-04984 Rev.*A
Page 11 of 200

11 Page







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