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PDF S6E2DH5G0A Data sheet ( Hoja de datos )

Número de pieza S6E2DH5G0A
Descripción Microcontroller
Fabricantes Cypress Semiconductor 
Logotipo Cypress Semiconductor Logotipo



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No Preview Available ! S6E2DH5G0A Hoja de datos, Descripción, Manual

S6E2DH Series
32-bit ARM® Cortex®-M4F
FM4 Microcontroller
Devices in the S6E2DH Series are highly integrated 32-bit microcontrollers with high performance and competitive cost. This series
is based on the ARM Cortex-M4F Processor with on-chip Flash memory and SRAM. The series has peripheral functions such as
graphics engine, display controller, motor control timers, ADCs, and Communication Interfaces (USB, CAN, UART, CSIO, I2C, LIN).
The products that are described in this data sheet are TYPE4-M4 category products. See the FM4 Family Peripheral Manual Main
Part (002-04856).
Features
32-bit ARM Cortex-M4F Core
Processor version: r0p1
Up to 160 MHz frequency operation
Built-in FPU
Supports DSP instructions
Memory Protection Unit (MPU): improves the reliability of an
embedded system
Integrated Nested Vectored Interrupt Controller (NVIC): 1
NMI (non-maskable interrupt) and 128 peripheral interrupts
and 16 priority levels
24-bit system timer (Sys Tick): System timer for OS task
management
On-Chip Memories
Flash memory
This series has on-chip flash memory with these features:
384 Kbytes
Built-in Flash Accelerator System with 16 Kbytes trace
buffer memory
Security function for code protection
Notes:
The read access to flash memory can be achieved
without wait-cycle up to operation frequency of 72 MHz.
Even at the operation frequency more than 72 MHz, an
equivalent access to flash memory can be obtained by
Flash Accelerator System.
SRAM
This is composed of two independent SRAMs (SRAM0 and
SRAM2). SRAM0 is connected to I-code bus and D-code bus
of Cortex-M4F core. SRAM2 is connected to the system bus of
Cortex-M4F core.
SRAM0: 32 Kbytes
SRAM2: 4 Kbytes
VRAM
This series is equipped with a SRAM for GDC.
Max 512 Kbytes
VFLASH
S6E2DH5GJA is equipped with a Flash for GDC.
2 Mbytes
External Bus Interface
Supports SRAM, NOR, NAND Flash and SDRAM devices
Up to two chip selects CS0 and CS8 (CS8 is only for
SDRAM)
8-/16-bit data width
Up to 25-bit address bit
Maximum area size : Up to 256 Mbytes
Supports address/data multiplexing
Supports external RDY function
Supports the scramble function
Possible to set the validity/invalidity of the scramble
function for the external areas 0x6000_0000 to
0x7FFF_FFFF in 4 Mbytes units.
Possible to set two kinds of the scramble key.
Note: It is necessary to prepare the dedicated software
library to use the scramble function.
USB Interface (One channel)
A USB interface is composed of device and host.
USB device
USB2.0 Full-Speed supported
Max 6 EndPoint supported
EndPoint 0 is for control transfer
EndPoint 1, 2 can be selected for bulk-transfer,
interrupt-transfer or isochronous-transfer
EndPoint 3 to 5 can select bulk-transfer or
interrupt-transfer
EndPoint 1 to 5 comprise the double buffer
The size of each endpoint is as follows.
Endpoint 0, 2 to 5: 64 bytes
EndPoint 1: 256 bytes
USB host
USB2.0 Full-Speed / Low-Speed supported
Bulk-transfer, interrupt-transfer and isochronous-transfer
support
USB device connected/disconnected automatically detect
In/out token handshake packet automatically accepted
Max 256-byte packet-length supported
Wake-up function supported
Cypress Semiconductor Corporation
Document Number: 002-05038 Rev.*A
• 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Revised March 4, 2016

1 page




S6E2DH5G0A pdf
S6E2DH Series
Table of Contents
Features................................................................................................................................................................................... 1
1. Product Lineup.................................................................................................................................................................. 7
2. Packages ........................................................................................................................................................................... 8
3. Pin Assignment ................................................................................................................................................................. 9
4. Pin Descriptions.............................................................................................................................................................. 13
5. I/O Circuit Type................................................................................................................................................................ 47
6. Handling Precautions ..................................................................................................................................................... 54
6.1 Precautions for Product Design ................................................................................................................................... 54
6.2 Precautions for Package Mounting.............................................................................................................................. 55
6.3 Precautions for Use Environment ................................................................................................................................ 57
7. Handling Devices ............................................................................................................................................................ 58
8. Block Diagram ................................................................................................................................................................. 61
9. Memory Size .................................................................................................................................................................... 62
10. Memory Map .................................................................................................................................................................... 62
11. Pin Status in Each CPU State ........................................................................................................................................ 64
12. Electrical Characteristics ............................................................................................................................................... 72
12.1 Absolute Maximum Ratings......................................................................................................................................... 72
12.2 Recommended Operating Conditions.......................................................................................................................... 73
12.3 DC Characteristics....................................................................................................................................................... 77
12.3.1 Current Rating.............................................................................................................................................................. 77
12.3.2 Pin Characteristics ....................................................................................................................................................... 87
12.4 AC Characteristics....................................................................................................................................................... 88
12.4.1 Main Clock Input Characteristics.................................................................................................................................. 88
12.4.2 Sub Clock Input Characteristics ................................................................................................................................... 89
12.4.3 Built-in CR Oscillation Characteristics.......................................................................................................................... 89
12.4.4 Operating Conditions of Main PLL (In the Case of Using Main Clock for Input Clock of PLL)...................................... 90
12.4.5 Operating Conditions of USB/I2S/GDC PLL (In the Case of Using Main Clock for Input Clock of PLL) ....................... 90
12.4.6 Operating Conditions of Main PLL (In the Case of Using Built-in High-Speed CR Clock for Input Clock
of Main PLL)................................................................................................................................................................. 91
12.4.7 Reset Input Characteristics .......................................................................................................................................... 91
12.4.8 Power-on Reset Timing................................................................................................................................................ 92
12.4.9 GPIO Output Characteristics........................................................................................................................................ 92
12.4.10 External Bus Timing.................................................................................................................................................. 93
12.4.11 Base Timer Input Timing......................................................................................................................................... 104
12.4.12 CSIO Timing ........................................................................................................................................................... 105
12.4.13 External Input Timing.............................................................................................................................................. 138
12.4.14 Quadrature Position/Revolution Counter Timing .................................................................................................... 139
12.4.15 I2C Timing............................................................................................................................................................... 142
12.4.16 SD Card Interface Timing ....................................................................................................................................... 144
12.4.17 ETM Timing ............................................................................................................................................................ 146
12.4.18 JTAG Timing........................................................................................................................................................... 147
12.4.19 I2S Timing ............................................................................................................................................................... 148
12.4.20 GDC:Panel Output Timing ...................................................................................................................................... 153
12.4.21 GDC: SDRAM-IF Timing......................................................................................................................................... 154
12.4.22 GDC: High-Speed Quad SPI Timing....................................................................................................................... 156
12.4.23 GDC: HyperBus I/F Timing ..................................................................................................................................... 158
Document Number: 002-05038 Rev.*A
Page 5 of 183

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S6E2DH5G0A arduino
LQP176
(TOP VIEW)
S6E2DH Series
VCC
PA0/GE_SDCKE
PA1/GE_SDCLK
PA2/GE_SDDQ31
PA3/GE_SDDQ30
P3B/TIOA0_1/INT04_1/AIN0_1/I2SMCLK0_0/RTO00_0/MAD10_0
P3C/SCS70_0/TIOA1_1/INT05_1/BIN0_1/I2SDO0_0/RTO01_0/MAD09_0
P3D/SIN7_0/TIOA2_1/INT06_1/ZIN0_1/I2SWS0_0/RTO02_0/MAD08_0
P3E/SOT7_0/TIOA3_1/INT07_1/I2SDI0_0/RTO03_0/MAD07_0
P3F/SCK7_0/TIOA4_1/I2SCK0_0/RTO04_0/MAD06_0
P7C/TIOA5_1/RTO05_0/MWEX_0
P7B/ADTG_2/MOEX_0/GE_HBCSX1
PA8/GE_SDDQ29
PA9/GE_SDDQ28
PAA/GE_SDDQ27
PAB/GE_SDDQ26
PAC/GE_SDDQ25
PAD/GE_SDDQ24
P33/SIN6_0/INT00_1/S_DATA1_0
P34/SOT6_0/FRCK0_0/S_DATA0_0
P35/SCK6_0/IC03_0/S_CLK_0
P36/SCS60_0/INT01_1/IC02_0/S_CMD_0
VCC
VSS
P37/RX2_1/INT02_1/GE_HBRESETX/IC01_0/S_DATA3_0
P38/TX2_1/INT03_1/GE_HBINTX/IC00_0/S_DATA2_0
P39/ADTG_0/GE_HBRSTOX/DTTI0X_0/S_WP_0
P3A/GE_HBWPX/S_CD_0
PA4/GE_SDDQ23
PA5/GE_SDDQ22
PA6/GE_SDDQ21
PA7/GE_SDDQ20
P7A/GE_HBRWDS
P70/GE_SPCK/GE_HBCK
P71/GE_SPDQ0/GE_HBCSX0
P72/INT00_0/GE_SPDQ3/GE_HBDQ0
P73/INT01_0/GE_SPCSX0/GE_HBDQ1
P74/INT02_0/GE_SPDQ1/GE_HBDQ2
P75/INT03_0/GE_SPDQ2/GE_HBDQ3
P76/INT04_0/GE_HBDQ4
P77/INT05_0/GE_HBDQ5
P78/INT06_0/GE_HBDQ6
P79/INT07_0/GE_HBDQ7
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
176pin Package
132 VSS
131 P97/AN23/PNL_PD16/MCASX_0
130 P96/AN22/PNL_TSIG5/PNL_PD17/MRASX_0
129 PCD/GE_SDA6
128 PCC/GE_SDA7
127 PCB/GE_SDA8
126 PCA/GE_SDA9
125 P95/AN21/SCK1_1/PNL_TSIG6/PNL_PD18/MAD19_0
124 P94/AN20/SOT1_1/TRACED3/PNL_TSIG7/PNL_PD19/MAD20_0
123 P93/AN19/SIN1_1/TRACED2/INT09_1/PNL_TSIG8/PNL_PD20/MNREX_0/MAD21_0
122 P92/AN18/SCK0_1/TRACED1/PNL_TSIG9/PNL_PD21/MNWEX_0/MAD22_0
121 P91/AN17/SOT0_1/TRACED0/PNL_TSIG10/PNL_PD22/MNCLE_0/MAD23_0
120 P90/AN16/SIN0_1/TRACECLK/INT08_1/PNL_TSIG11/PNL_PD23/MNALE_0/MCLKOUT_0
119 P1F/AN15/SCK6_1/TIOB7_0/MADATA15_0
118 P1E/AN14/SOT6_1/TIOA7_0/RTO05_1/MADATA14_0
117 P1D/AN13/SIN6_1/TIOB6_0/INT15_0/RTO04_1/MADATA13_0
116 P1C/AN12/SCS60_1/TIOA6_0/INT14_0/RTO03_1/MADATA12_0
115 PC9/GE_SDA10
114 PC8/GE_SDA11
113 PC7/GE_SDBA0
112 PC6/GE_SDBA1
111 P1B/AN11/SCK5_0/TIOB5_0/ZIN0_2/RTO02_1/MADATA11_0
110 P1A/AN10/SOT5_0/TIOA5_0/BIN0_2/RTO01_1/MADATA10_0
109 P19/AN09/SIN5_0/TIOB4_0/INT13_0/AIN0_2/RTO00_1/MADATA09_0
108 P18/AN08/SCK3_0/TIOA4_0/IC03_1/MADATA08_0
107 P17/AN07/SOT3_0/TIOB3_0/IC02_1/MADATA07_0
106 P16/AN06/SIN3_0/TIOA3_0/INT12_0/IC01_1/MADATA06_0
105 P15/AN05/SCK2_0/TIOB2_0/INT11_0/IC00_1/MADATA05_0
104 P14/AN04/SOT2_0/TIOA2_0/DTTI0X_1/MADATA04_0
103 P13/AN03/SIN2_0/TIOB1_0/INT10_0/FRCK0_1/MADATA03_0
102 P12/AN02/SCK1_0/TIOA1_0/ZIN0_0/MADATA02_0
101 P11/AN01/SOT1_0/TIOB0_0/BIN0_0/MADATA01_0
100 P10/AN00/SIN1_0/TIOA0_0/INT09_0/AIN0_0/MADATA00_0
99 PC5/GE_SDDQ0
98 PC4/GE_SDDQ1
97 PC3/GE_SDDQ2
96 PC2/GE_SDDQ3
95 PC1/GE_SDDQ4
94 PC0/GE_SDDQ5
93 AVRH
92 AVRL
91 AVSS
90 AVCC
89 VCC
Note:
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
Document Number: 002-05038 Rev.*A
Page 11 of 183

11 Page







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