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PDF S29GL512T Data sheet ( Hoja de datos )

Número de pieza S29GL512T
Descripción MirrorBit Eclipse Flash Memory Devices
Fabricantes Cypress Semiconductor 
Logotipo Cypress Semiconductor Logotipo



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S29GL01GT, S29GL512T
1 Gbit (128 Mbyte), 512 Mbit (64 Mbyte)
GL-T MirrorBit® Eclipse™ Flash
General Description
The Cypress® S29GL01GT/512T are MirrorBit® Eclipse™ flash products fabricated on 45 nm process technology. These devices
offer a fast page access time as fast as 15 ns, with a corresponding random access time as fast as 100 ns. They feature a Write
Buffer that allows a maximum of 256 words/512 bytes to be programmed in one operation, resulting in faster effective programming
time than standard programming algorithms. This makes these devices ideal for today’s embedded applications that require higher
density, better performance, and lower power consumption.
Distinctive Characteristics
45 nm MirrorBit Eclipse Technology
Single supply (VCC) for read / program / erase (2.7 V to
3.6 V)
Versatile I/O feature
– Wide I/O voltage range (VIO): 1.65 V to VCC
x8/x16 data bus
Asynchronous 32-byte Page read
512-byte Programming Buffer
– Programming in Page multiples, up to a maximum of 512
bytes
Single word and multiple program on same word options
Automatic Error Checking and Correction (ECC) — internal
hardware ECC with single bit error correction
Sector Erase
– Uniform 128-kbyte sectors
Suspend and Resume commands for Program and Erase
operations
Status Register, Data Polling, and Ready/Busy pin methods
to determine device status
Advanced Sector Protection (ASP)
– Volatile and non-volatile protection methods for each
sector
Separate 2048-byte One Time Program (OTP) array
– Four lockable regions (SSR0 - SSR3)
– SSR0 is Factory Locked
– SSR3 is Password Read Protect
Common Flash Interface (CFI) parameter table
Temperature Range / Grade:
– Industrial (40 °C to +85 °C)
– Industrial Plus (40 °C to +105 °C)
– Extended (40 °C to +125 °C)
– Automotive, AEC-Q100 Grade 3 (–40 °C to +85 °C)
– Automotive, AEC-Q100 Grade 2 (–40 °C to +105 °C)
100,000 Program / Erase Cycles
20-year data retention
Packaging Options
– 56-pin TSOP
– 64-ball LAA Fortified BGA, 13 mm 11 mm
– 64-ball LAE Fortified BGA, 9 mm 9 mm
– 56-ball VBU Fortified BGA, 9 mm 7 mm
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 002-00247 Rev. *G
• San Jose, CA 95134-1709 • 408-943-2600
Revised October 27, 2016

1 page




S29GL512T pdf
S29GL01GT, S29GL512T
Table 1.1 S29GL-T Address Map
Type
Address within Page
Address within Write Buffer
Page
Write-Buffer-Line
Sector
Count
16
256
4096 per Sector
256 per Sector
1024 (1 Gb)
512 (512 Mb)
x16
Addresses
A3–A0
A7–A0
A15–A4
A15–A8
Amax–A16
Count
32
512
4096 per Sector
256 per Sector
1024 (1 Gb)
512 (512 Mb)
x8
Addresses
A3–A-1
A7–A-1
A15–A4
A15–A8
Amax–A16
The device control logic is subdivided into two parallel operating sections, the Host Interface Controller (HIC) and the Embedded
Algorithm Controller (EAC). HIC monitors signal levels on the device inputs and drives outputs as needed to complete read and write
data transfers with the host system. HIC delivers data from the currently entered address space on read transfers; places write
transfer address and data information into the EAC command memory; notifies the EAC of power transition, hardware reset, and
write transfers. The EAC looks in the command memory, after a write transfer, for legal command sequences and performs the
related Embedded Algorithms.
Changing the non-volatile data in the memory array requires a complex sequence of operations that are called Embedded
Algorithms (EA). The algorithms are managed entirely by the device internal EAC. The main algorithms perform programming and
erase of the main array data. The host system writes command codes to the flash device address space. The EAC receives the
commands, performs all the necessary steps to complete the command, and provides status information during the progress of an
EA.
The erased state of each memory bit is a logic 1. Programming changes a logic 1 (High) to a logic 0 (Low). Only an Erase operation
is able to change a 0 to a 1. An erase operation must be performed on an entire 128-kbyte aligned and length group of data call a
Sector. When shipped from Cypress all Sectors are erased.
Programming is done via a 512-byte Write Buffer. In x16 it is possible to write from 1 to 256 words, anywhere within the Write Buffer
before starting a programming operation. Within the flash memory array, each 512-byte aligned group of 512 bytes is called a Line.
In x8 it is possible to write from 1 to 256 bytes, anywhere within the Write Buffer before starting a program operation. A programming
operation transfers volatile data from the Write Buffer to a non-volatile memory array Line. The operation is called Write Buffer
Programming.
As the device transfers each 32-byte aligned page of data that was loaded into the Write buffer to the 512-byte Flash array line,
internal logic programs an ECC Code for the Page into a portion of the memory array not visible to the host system software. The
internal logic checks the ECC information during the initial access of every array read operation. If needed, the ECC information
corrects a one bit error during the initial access time.
The Write Buffer is filled with 1’s after reset or the completion of any operation using the Write Buffer. Any locations not written to a 0
by a Write to Buffer command are by default still filled with 1’s. Any 1’s in the Write Buffer do not affect data in the memory array
during a programming operation.
As each Page of data that was loaded into the Write Buffer is transferred to a memory array Line.
Sectors may be individually protected from program and erase operations by the Advanced Sector Protection (ASP) feature set.
ASP provides several, hardware and software controlled, volatile and non-volatile, methods to select which sectors are protected
from program and erase operations.
Document Number: 002-00247 Rev. *G
Page 5 of 105

5 Page





S29GL512T arduino
S29GL01GT, S29GL512T
2.7 ECC Status ASO
The system can access the ECC Status ASO by issuing the ECC Status entry command sequence during Read Mode. The ECC
Status ASO provides the enabled or disabled status of the ECC function or if the ECC function corrected a single-bit Error when
reading the selected Page. Section 5.3, Automatic ECC on page 21 describes the ECC function in more detail.
The ECC Status ASO allows the following activities:
Read ECC Status for the selected Page.
ASO Exit.
2.7.1 ECC Status
The contents of the ECC Status ASO indicate, for the selected ECC Page, whether the ECC logic has corrected an error in the ECC
Page eight bit ECC code, in the ECC page of 32-bytes of data, or that ECC is disabled for that ECC unit. The address specified in
the ECC Status Read Command, provided in Table 7.1 on page 48 and Table 7.2 on page 51, selects the ECC Page.
Table 2.5 ECC Status Word – Upper Byte
Bit
Name
Value
15
RFU
X
14
RFU
X
13
RFU
X
12
RFU
X
11
RFU
X
10
RFU
X
9
RFU
X
8
RFU
X
Table 2.6 ECC Status Word – Lower Byte
Bit
Name
7
RFU
6
RFU
5
RFU
4
RFU
3
ECC Enabled on
16-Word Page
Value
X
X
X
X
0=ECC Enabled
1=ECC Disabled
2
Single Bit Error
Corrected ECC Bits
0=No Error Corrected
1=Single Bit Error
Corrected
1
Single Bit Error Corrected
Data Bits
0
RFU
0=No Error Corrected
1=Single Bit Error Corrected
X
Document Number: 002-00247 Rev. *G
Page 11 of 105

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