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PDF S25FS064S Data sheet ( Hoja de datos )
| Número de pieza | S25FS064S | |
| Descripción | 64 Mbit (8 Mbyte) 1.8-V FS-S Flash | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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PRELIMINARY
S25FS064S
64 Mbit (8 Mbyte), 1.8-V FS-S Flash
Features
Serial Peripheral Interface (SPI) with Multi-I/O
– SPI Clock polarity and phase modes 0 and 3
– Double Data Rate (DDR) option
– Extended Addressing - 24 or 32-bit address options
– Serial Command subset and footprint compatible with S25FL1-K,
S25FL-P and S25FL-S SPI families
– Multi I/O Command subset and footprint compatible with
S25FL1-K S25FL-P and S25FL-S SPI families
Read
– Commands: Normal, Fast, Dual Output, Dual I/O, Quad Output,
Quad I/O, DDR Quad I/O
– Modes: Burst Wrap, Continuous (XIP), QPI (QPI)
– Serial Flash Discoverable Parameters (SFDP) and Common Flash
Interface (CFI), for configuration information.
Program
– 256 or 512 Bytes Page Programming buffer
– Program suspend and resume
– Automatic ECC -internal hardware Error Correction Code
generation with single bit error correction
Erase
– Hybrid sector option
– Physical set of eight 4KB sectors and one 32KB sector at the top
or bottom of address space with all remaining sectors of 64KB
– Uniform sector option
– Uniform 64KB or 256KB blocks for software compatibility with
higher density and future devices
– Erase suspend and resume
– Erase status evaluation
– 100,000 Program-Erase Cycles on any sector, minimum
– 20 Year Data Retention, minimum
Security Features
– One Time Program (OTP) array of 1024 bytes
– Block Protection:
– Status Register bits to control protection against program or erase
of a contiguous range of sectors.
– Hardware and software control options
– Advanced Sector Protection (ASP)
– Individual sector protection controlled by boot code or password
– Option for password control of read access
Technology
– Cypress 65 nm MirrorBit® Technology with Eclipse Architecture
Single Supply Voltage with CMOS I/O
– 1.7V to 2.0V
Temperature Range
– Industrial (40°C to +85°C)
– Industrial Plus (40°C to +105°C)
– Extended (40°C to +125°C)
Packages (all Pb-free)
– 8-lead SOIC 208 mil (SOC008)
– LGA 5x6 mm (W9A008)
– BGA-24 6 8 mm
– 5 5 ball (FAB024) footprint
Logic Block Diagram
CS#
SCK
SI/IO0
SRAM
MirrorBit Array
SO/IO1
WP#/IO2
RESET#/IO3
RESET#
I/O
Control
Logic
Y Decoders
Data Latch
Data Path
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 002-03631 Rev. *C
• San Jose, CA 95134-1709 • 408-943-2600
Revised June 24, 2016
1 page  
PRELIMINARY
S25FS064S
Table 1.1 Cypress SPI Families Comparison (Continued)
Parameter
Auto Boot Mode
Erase Suspend/Resume
Program Suspend/Resume
Operating Temperature
FS-S
No
Yes
Yes
-40 °C to +85 °C / +105 °C
FS-S
No
Yes
Yes
-40 °C to +85 °C / +105 °C /
+125° C
FL-S
Yes
Yes
Yes
-40 °C to +85 °C / +105 °C
FL-P
No
No
No
-40 °C to +85 °C/+105 °C
Notes:
– FL-P column indicates FL129P MIO SPI device (for 128Mb density), FL128P does not support MIO, OTP, or 4KB sectors
– 64KB sector erase option only for 128Mb/256Mb density FL-P, FL-S and FS-S devices
– Refer to individual data sheets for further details
1.2.2 Known Differences from Prior Generations
1.2.2.1
Error Reporting
FL-K and FL-P memories either do not have error status bits or do not set them if program or erase is attempted on a protected
sector. The FS-S and FL-S families do have error reporting status bits for program and erase operations. These can be set when
there is an internal failure to program or erase, or when there is an attempt to program or erase a protected sector. In these cases
the program or erase operation did not complete as requested by the command. The P_ERR or E_ERR bits and the WIP bit will be
set to and remain 1 in SR1V. The clear status register command must be sent to clear the errors and return the device to standby
state.
1.2.2.2
Secure Silicon Region (OTP)
The FS-S size and format (address map) of the One Time Program area is different from FL-K and FL-P generations. The method
for protecting each portion of the OTP area is different. For additional details see Secure Silicon Region (OTP) on page 64.
1.2.2.3
Configuration Register Freeze Bit
The configuration register-1 Freeze Bit CR1V[0], locks the state of the Block Protection bits (SR1NV[4:2] and SR1V[4:2]),
TBPARM_O bit (CR1NV[2]), and TBPROT_O bit (CR1NV[5]), as in prior generations. In the FS-S and FL-S families the Freeze Bit
also locks the state of the configuration register-1 BPNV_O bit (CR1NV[3]), and the Secure Silicon Region (OTP) area.
1.2.2.4
Sector Erase Commands
The command for erasing a 4KBytes sector is supported only for use on 4KBytes parameter sectors at the top or bottom of the FS-S
device address space.
The command for erasing an 8KByte area (two 4KBytes sectors) is not supported.
The command for erasing a 32KByte area (eight 4KBytes sectors) is not supported.
The sector erase command (SE) for FS-S 64KBytes sectors is supported when the configuration option for uniform 64KBytes sector
is selected or, when the hybrid configuration option for 4KBytes parameter sectors with 64KBytes uniform sectors is used. When the
hybrid option is in use, the 64KBytes erase command may be used to erase the 32KBytes of address space adjacent to the group of
eight 4KBytes sectors. The 64KBytes erase command in this case is erasing the 64KBytes sector that is partially overlaid by the
group of eight 4KBytes sectors without affecting the 4KBytes sectors. This provides erase control over the 32KBytes of address
space without also forcing the erase of the 4KBytes sectors. This is different behavior than implemented in the FL-S family. In the
FL-S family, the 64KBytes sector erase command can be applied to a 64KBytes block of 4KBytes sectors to erase the entire block of
parameter sectors in a single operation. In the FS-S, the parameter sectors do not fill an entire 64KBytes block so only the 4KBytes
parameter sector erase (20h) is used to erase parameter sectors.
The erase command for a 256KBytes sector replaces the 64KBytes erase command when the configuration option for 256 KBytes
uniform logical sectors is used.
Document Number: 002-03631 Rev. *C
Page 5 of 147
5 Page 
PRELIMINARY
S25FS064S
Figure 3.3 Bus Master and Memory Devices on the SPI Bus - Quad Bit Data Path - Separate RESET#
RESET#
IO3
IO2
IO1
IO0
SCK
RESET#
IO3
IO2
IO1
IO0
SCK
CS2#
CS1#
CS#
CS#
SPI
Bus Master
SPI Flash
SPI Flash
Figure 3.4 Bus Master and Memory Devices on the SPI Bus - Quad Bit Data Path - I/O3_RESET#
IO3 / RESET#
IO2
IO1
IO0
SCK
IO3_RESET#
IO2
IO1
IO0
SCK
CS#
SPI
Bus Master
CS#
SPI Flash
Document Number: 002-03631 Rev. *C
Page 11 of 147
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