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PDF CD22402E Data sheet ( Hoja de datos )
| Número de pieza | CD22402E | |
| Descripción | Sync Generator for TV Applications and Video Processing Systems | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de CD22402E (archivo pdf) en la parte inferior de esta página. Total 11 Páginas | ||
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May 1999
Semiconductor
CD22402NO
Call
CRoeErnOCetrOBmaSMlaOAiMl:pLEpEcNlTeiDcnEaEtaPtDipoRpRnO@sEDP1hUL-aC8Ar0rTCi0sE-.4cM4o2Em-N7T74S7yncanGdenVeidraetoorPfroorceTsVsAinpgpSlicyasttieomnss
[ /Title
(CD2240
2)
/Subject
(Sync
Genera-
tor for
TV
Applica-
tions and
Video
Process-
Features
• Interlaced Composite Sync Output
• Automatic Genlock Capability
• Crystal Oscillator Operation
• 525 or 625 Line Operation
• Vertical Reset Option
• Wide Power Supply Operating Voltage . . . . . 4V to 15V
Applications
• Cameras
• Monitors and Displays
• CATV
• Teletext
• Video Games
• Sync Restorer
• Video Service Instruments
Part Number Information
PART NUMBER
CD22402D
CD22402E
TEMP.
RANGE (oC)
PACKAGE
-55 to 125 24 Ld SBDIP
-40 to 85 24 Ld PDIP
PKG.
NO.
D24.6
E24.6
Description
The Harris CD22402 (Note) is a CMOS LSI sync generator that
produces all the timing signals required to drive a fully 2-to-1
interlaced 525-line 30-frame/second, or 625-line 25-frame/sec-
ond TV camera or video processing system. A complete sync
waveform is produced which begins each field with six serrated
vertical sync pulses, preceded and followed by six half-width
double frequency equalizing pulses. The sync output is gated by
the master clock to preserve horizontal phase continuity during
the vertical interval.
The CD22402 can be operated either in “genlock” mode, in
which it is synchronized with a reference sync pulse train from
another TV camera, or in “stand-alone” mode, in which it is syn-
chronized with a local on-chip crystal oscillator (the crystal and
two passive components are off chip). Also, the circuit can
sense the presence or absence of a reference sync pulse train
and automatically select the “genlock” or “stand-alone” mode.
A frame sync pulse is produced at the beginning of every odd
field. The vertical counter can be reset to either the first equalizing
pulse or the first vertical sync pulse of the vertical interval. The
interlaced sync provided by the CD22402 differs from RS-170 by
having slightly narrower sync and equalizing pulses. The clock
frequency of 32 times horizontal rate allows for approximately 4µs
horizontal pulse widths and 2µs equalizing pulses. Otherwise
operation can be phase locked to a color sub-carrier for a full
interlaced operating system.
The CD22402 is operable with a single supply over a voltage
range of 4V to 15V.
Pinout
CD22402 (PDIP, SBDIP)
TOP VIEW
DELAY, GENLOCK TO CRYSTAL OSCILLATOR 1
CRYSTAL OSCILLATOR FEEDBACK TAP 2
VSS 3
HORIZONTAL DRIVE OUTPUT 4
MIXED SYNC OUTPUT 5
GENLOCK OSCILLATOR CAPACITOR CONNECTION 6
MIXED BEAM BLANKING OUTPUT 7
VERTICAL COUNTER RESET TO FIRST EQUALIZING PULSE 8
VERTICAL DRIVE OUTPUT 9
VERTICAL RESET TO FIRST VERTICAL SYNC PULSE 10
HORIZONTAL CLAMP OUTPUT 11
VSS 12
24 RESISTOR CONNECTION FOR GENLOCK OSCILLATOR
23 MASTER FREQUENCY INPUT
22 R-C CONNECTION FOR GENLOCK OSCILLATOR
21 DELAY, GENLOCK TO CRYSTAL OSCILLATOR
20 GENLOCK INPUT (COMPOSITE SYNC)
19 VDD
18 525 LINE TO 625 LINE OPERATION SWITCH
17 VERTICAL PROCESSING BLANKING OUTPUT
16 SHORT VERTICAL DRIVE OUTPUT
15 FRAME SYNC OUTPUT (ODD FIELD)
14 HORIZONTAL PROCESSING BLANKING OUTPUT
13 MIXED PROCESSING BLANKING OUTPUT
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1999
8-40
File Number 1686.5
1 page  
CD22402
Switching Electrical Specifications TA = 25oC and CL = 15pF. Typical Temperature Coefficient for All Values of VDD = 0.3%/oC
TEST
CONDITIONS
PARAMETER (NOTE 4)
Output State Propagation Delay Time (50% to 50%)
SYMBOL
VDD (V)
MIN TYP MAX UNITS
Low-to-High Level
High-to-Low Level
Output State Transition Time (10% to 90%)
tPLH
tPHL
5 - 40 80 ns
10 - 20 40 ns
Low-to-High
tTLH
5-
High-to-Low
tTHL
10 -
Input Capacitance (Per Input)
CI - -
NOTE:
4. The characteristics given are defined for unbuffered gate in the CMOS process of the CD22402.
45 90 ns
30 60 ns
5 - pF
Logic Diagram
VERTICAL DRIVE (VERT. RESET
TO FIRST VERT. PULSE)
INTEGRATOR
10
+
RQ
SQ
22 10K
10K 24
GENLOCK OSC.
51pF
6
GENLOCK
SYNC
HOR.
DR
20
SQ
RQ
1M 1N914
0.001µF
(NOTE 5)
21
1
(NOTE 6)
CRYSTAL
32 TIMES
HORIZ.
503.496kHz
100pF
23
1M
2
HOR. PROCESS
BLANKING
NOTES:
5. Pin 21 high when pin 20 is high (or open).
6. Pin 1 high inhibits clock.
FIGURE 1. DETAIL OF THE OSCILLATOR/GENLOCK PORTION OF THE CD22402
CLOCK TO
COUNTERS
8-44
5 Page 
CD22402
100kΩ
3.3µF 10kΩ
75Ω
2
-
31
+
1
0.5 TO 2VP-P
VIDEO SIGNAL IN
VCC = +5
GND
VSS VDD
2kΩ
10µF 2kΩ
1kΩ
0.1µF
0.0022µF
2MΩ
100kΩ
1N914
10µF
13
-
12
4
+
14
5
+
2
6-
7
10kΩ
NEG. HORIZ. SYNC OUT
(TO PIN 20 - CD22402)
POS. HORIZ. SYNC OUT
0.0022µF
0.0022µF
10kΩ
9
-
10 3
+
8
NEG. VERTICAL SYNC OUT
(TO PIN 10 - CD22402)
CA5470 BIMOS-E QUAD OP AMP
PIN 4 TO +5V (VDD)
PIN 11 TO GND (VSS)
NOTE: The genlock input to pins 10 and 20 of the CD22402 are direct coupled to the output from Pins 8 and 14 of the CA5470. Refer to
Application Note AN-8742 for additional information.
FIGURE 12. SUGGESTED SYNC-SEPARATOR CIRCUIT USING THE CA5470 BIMOS-E QUAD OP AMP IN THE VDD RANGE
OF 4V TO 12V
8-50
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet CD22402E.PDF ] | |
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