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PDF CAT5269 Data sheet ( Hoja de datos )
| Número de pieza | CAT5269 | |
| Descripción | Dual Digital Potentiometer | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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CAT5269
Dual Digital
Potentiometer (POT)
with 256 Taps
and 2‐wire Interface
Description
The CAT5269 is two digital POTs integrated with control logic and
18 bytes of NVRAM memory. Each digital POT consists of a series of
resistive elements connected between two externally accessible end
points. The tap points between each resistive element are connected to
the wiper outputs with CMOS switches. A separate 8-bit control
register (WCR) independently controls the wiper tap switches for each
digital POT. Associated with each wiper control register are four 8-bit
non-volatile memory data registers (DR) used for storing up to four
wiper settings. Writing to the wiper control register or any of the
non-volatile data registers is via a 2-wire serial bus. On power-up, the
contents of the first data register (DR0) for each of the potentiometers
is automatically loaded into its respective wiper control registers.
The CAT5269 can be used as a potentiometer or as a two terminal,
variable resistor. It is intended for circuit level or system level
adjustments in a wide variety of applications. It is available in the
−40C to 85C industrial operating temperature range and offered in a
24-lead SOIC and TSSOP package.
Features
Four Linear Taper Digital Potentiometers
256 Resistor Taps per Potentiometer
End to End Resistance 50 kW or 100 kW
Potentiometer Control and Memory Access via 2-wire Interface
(I2C like)
Low Wiper Resistance, Typically 100 W
Nonvolatile Memory Storage for up to Four Wiper Settings for Each
Potentiometer
Automatic Recall of Saved Wiper Settings at Power Up
2.5 to 6.0 Volt Operation
Standby Current less than 1 mA
1,000,000 Nonvolatile WRITE Cycles
100 Year Nonvolatile Memory Data Retention
24-lead SOIC and TSSOP Packages
Industrial Temperature Range
These Devices are Pb-Free, Halogen Free/BFR Free and are RoHS
Compliant
http://onsemi.com
TSSOP−24
Y SUFFIX
CASE 948AR
SOIC−24
W SUFFIX
CASE 751BK
PIN CONNECTIONS
NC
A0
NC
NC
NC
NC
VCC
RL0
RH0
RW0
A2
WP
1
CAT5269
SOIC−24 (W)
TSSOP−24 (Y)
(Top View)
A3
SCL
NC
NC
NC
NC
GND
RW1
RH1
RL1
A1
SDA
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 13 of this data sheet.
Semiconductor Components Industries, LLC, 2013
July, 2013 − Rev. 7
1
Publication Order Number:
CAT5269/D
1 page  
CAT5269
Table 5. D.C. OPERATING CHARACTERISTICS (VCC = +2.5 V to +6.0 V, unless otherwise specified.)
Symbol
Parameter
Test Conditions
Min
ICC1
ICC2
ISB
ILI
ILO
VIL
VIH
VOL1
Power Supply Current
Power Supply Current
Non-volatile WRITE
Standby Current (VCC = 5 V)
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage (VCC = 3 V)
fSCL = 400 kHz, SDA = Open
VCC = 6 V, Inputs = GND
fSCK = 400 kHz, SDA Open
VCC = 6 V, Input = GND
VIN = GND or VCC, SDA = Open
VIN = GND to VCC
VOUT = GND to VCC
IOL = 3 mA
−1
VCC x 0.7
Max
1
5
5
10
10
VCC x 0.3
VCC + 1.0
0.4
Table 6. CAPACITANCE (TA = 25C, f = 1.0 MHz, VCC = 5 V)
Symbol
Test
CI/O (Note 8)
CIN (Note 8)
Input/Output Capacitance (SDA)
Input Capacitance (A0, A1, A2, A3, SCL, WP)
Conditions
VI/O = 0 V
VIN = 0 V
Max
8
6
Table 7. A.C. CHARACTERISTICS
Symbol
Parameter
fSCL Clock Frequency
TI (Note 8)
Noise Suppression Time Constant at SCL, SDA Inputs
tAA SLC Low to SDA Data Out and ACK Out
tBUF (Note 8) Time the bus must be free before a new transmission can start
tHD:STA
Start Condition Hold Time
tLOW
Clock Low Period
tHIGH
Clock High Period
tSU:STA
Start Condition Setup Time (for a Repeated Start Condition)
tHD:DAT
Data in Hold Time
tSU:DAT
Data in Setup Time
tR (Note 8)
SDA and SCL Rise Time
tF (Note 8)
SDA and SCL Fall Time
tSU:STO
Stop Condition Setup Time
tDH Data Out Hold Time
8. This parameter is tested initially and after a design or process change that affects the parameter.
2.5 V − 6.0 V
Min Max
400
200
1
1.2
0.6
1.2
0.6
0.6
0
50
0.3
300
0.6
100
Units
mA
mA
mA
mA
mA
V
V
V
Units
pF
pF
Units
kHz
ns
ms
ms
ms
ms
ms
ms
ns
ns
ms
ns
ms
ns
http://onsemi.com
5
5 Page 
CAT5269
These instructions are:
XFR Data Register to Wiper Control Register −
This transfers the contents of one specified Data
Register to the associated Wiper Control Register.
XFR Wiper Control Register to Data Register −
This transfers the contents of the specified Wiper
Control Register to the specified associated Data
Register.
Gang XFR Data Register to Wiper Control
Register − This transfers the contents of all specified
Data Registers to the associated Wiper Control
Registers.
Gang XFR Wiper Counter Register to Data
Register − This transfers the contents of all Wiper
Control Registers to the specified associated Data
Registers.
Increment/Decrement Command
The final command is Increment/Decrement (Figures 12
and 13). The Increment/Decrement command is different
from the other commands. Once the command is issued and
the CAT5269 has responded with an acknowledge, the
master can clock the selected wiper up and/or down in one
segment steps; thereby providing a fine tuning capability to
the host. For each SCL clock pulse (tHIGH) while SDA is
HIGH, the selected wiper will move one resistor segment
towards the RH terminal. Similarly, for each SCL clock
pulse while SDA is LOW, the selected wiper will move one
resistor segment towards the RL terminal.
See Instructions format for more detail.
SDA
010 1
S ID3 ID2 ID1 ID0 A3 A2 A1 A0
T
A
R
Device ID
T
Internal
Address
CAK
I3
I2
I1
I0
R1 R0 P1 P0
A
C
Instruction
Opcode
K
Register Pot/WCR
Address Address
Figure 10. Two-byte Instruction Sequence
S
T
O
P
SDA
0 101
S
T
ID3
ID2 ID1 ID0 A3
A2
A1 A0
A
R
Device ID
T
Internal
Address
CAK
I3 I2 I1 I0
Instruction
Opcode
R1 R0
Data
Register
P1 P0 CAK
Pot/WCR
Address
Address
D7 D6 D5 D4 D3 D2 D1 D0
WCR[7:0]
or
Data Register D[7:0]
CAK
S
T
O
P
Figure 11. Three-byte Instruction Sequence
SDA
0101
S ID3 ID2 ID1 ID0 A3 A2 A1 A0
AT Device ID
Internal
R Address
T
A I3 I2 I1 I0 R1 R0 P1 P0 A
C
K
Instruction
Opcode
Data
Register
Pot/WCR
Address
CK
Address
I
NC
1
I
NC
2
Figure 12. Increment/Decrement Instruction Sequence
INC/DEC
Command
Issued
SCL
tWRL
I
NC
n
D
CE
1
D
CE
n
S
OPT
SDA
RW Voltage Out
Figure 13. Increment/Decrement Timing Limits
http://onsemi.com
11
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet CAT5269.PDF ] | |
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