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PDF CAT5259 Data sheet ( Hoja de datos )
| Número de pieza | CAT5259 | |
| Descripción | Quad Digital Potentiometer | |
| Fabricantes | ON Semiconductor | |
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CAT5259
Quad Digital
Potentiometer (POT)
with 256 Taps
and I2C Interface
Description
The CAT5259 is four digital POTs integrated with control logic and
16 bytes of NVRAM memory. Each digital POT consists of a series of
resistive elements connected between two externally accessible end
points. The tap points between each resistive element are connected to
the wiper outputs with CMOS switches. A separate 8-bit control
register (WCR) independently controls the wiper tap switches for each
digital POT. Associated with each wiper control register are four 8-bit
non-volatile memory data registers (DR) used for storing up to four
wiper settings. Writing to the wiper control register or any of the
non-volatile data registers is via a I2C serial bus. On power-up, the
contents of the first data register (DR0) for each of the four
potentiometers is automatically loaded into its respective wiper
control registers.
The CAT5259 can be used as a potentiometer or as a two terminal,
variable resistor. It is intended for circuit level or system level
adjustments in a wide variety of applications. It is available in the 0C
to 70C commercial and −40C to 85C industrial operating
temperature ranges and offered in a 24-lead SOIC and TSSOP
package.
Features
Four Linear Taper Digital Potentiometers
256 Resistor Taps per Potentiometer
End to End Resistance 50 kW or 100 kW
Potentiometer Control and Memory Access via I2C Interface
Low Wiper Resistance, Typically 100 W
Nonvolatile Memory Storage for up to Four Wiper Settings for
Each Potentiometer
Automatic Recall of Saved Wiper Settings at Power Up
2.5 to 6.0 V Operation
Standby Current less than 1 mA
1,000,000 Nonvolatile WRITE Cycles
100 Year Nonvolatile Memory Data Retention
24-lead SOIC and 24-lead TSSOP Packages
Industrial Temperature Range
These Devices are Pb-Free, Halogen Free/BFR Free and are
RoHS Compliant
http://onsemi.com
TSSOP−24
Y SUFFIX
CASE 948AR
SOIC−24
W SUFFIX
CASE 751BK
PIN CONNECTIONS
NC
A0
RW3
RH3
RL3
NC
VCC
RL0
RH0
RW0
A2
WP
1
CAT5259
SOIC−24 (W)
TSSOP−24 (Y)
(Top View)
A3
SCL
RL2
RH2
RW2
NC
GND
RW1
RH1
RL1
A1
SDA
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 13 of this data sheet.
Semiconductor Components Industries, LLC, 2013
July, 2013 − Rev. 11
1
Publication Order Number:
CAT5259/D
1 page  
CAT5259
Table 5. D.C. OPERATING CHARACTERISTICS (VCC = +2.5 V to +6.0 V, unless otherwise specified.)
Symbol
Parameter
Test Conditions
Min
ICC1 Power Supply Current
ICC2 Power Supply Current
Non-volatile WRITE
fSCL = 400 kHz, SDA = Open
VCC = 6 V, Inputs = GND
fSCK = 400 kHz, SDA Open
VCC = 6 V, Input = GND
ISB
ILI
ILO
VIL
VIH
VOL1
Standby Current (VCC = 5 V)
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage (VCC = 3 V)
VIN = GND or VCC, SDA = Open
VIN = GND to VCC
VOUT = GND to VCC
IOL = 3 mA
−1
VCC x 0.7
Max
1
5
5
10
10
VCC x 0.3
VCC + 1.0
0.4
Table 6. CAPACITANCE (TA = 25C, f = 1.0 MHz, VCC = 5 V)
Symbol
Test
CI/O (Note 8)
CIN (Note 8)
Input/Output Capacitance (SDA)
Input Capacitance (A0, A1, A2, A3, SCL, WP)
Conditions
VI/O = 0 V
VIN = 0 V
Max
8
6
Table 7. A.C. CHARACTERISTICS
Symbol
fSCL
TI (Note 8)
tAA
tBUF (Note 8)
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR (Note 8)
tF (Note 8)
tSU:STO
tDH
Parameter
Clock Frequency
Noise Suppression Time Constant at SCL, SDA Inputs
SLC Low to SDA Data Out and ACK Out
Time the bus must be free before a new transmission can start
Start Condition Hold Time
Clock Low Period
Clock High Period
Start Condition SetupTime (for a Repeated Start Condition)
Data in Hold Time
Data in Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
2.5 V − 6.0 V
Min Max
400
200
1
1.2
0.6
1.2
0.6
0.6
0
50
0.3
300
0.6
100
Table 8. POWER UP TIMING (Notes 8, 9)
Symbol
Parameter
tPUR
Power-up to Read Operation
tPUW
Power-up to Write Operation
8. This parameter is tested initially and after a design or process change that affects the parameter.
9. tPUR and tPUW are delays required from the time VCC is stable until the specified operation can be initiated.
Table 9. WIPER TIMING
Symbol
Parameter
Min
tWRPO
tWRL
Wiper Response Time After Power Supply Stable
Wiper Response Time After Instruction Issued
5
5
Max
1
1
Max
10
10
Units
mA
mA
mA
mA
mA
V
V
V
Units
pF
pF
Units
kHz
ns
ms
ms
ms
ms
ms
ms
ns
ns
ms
ns
ms
ns
Units
ms
ms
Units
ms
ms
http://onsemi.com
5
5 Page 
INC/DEC
Command
Issued
SCL
SDA
CAT5259
tWRID
Voltage Out
RW
Figure 13. Increment/Decrement Timing Limits
INSTRUCTION FORMAT
Table 14. READ WIPER CONTROL REGISTER (WCR)
S DEVICE ADDRESSES A
INSTRUCTION
A
DATA
AS
T
A
0 1 0 1 A3
A2
A1
A0
C
K
1
0
0
1
0
0
P1
P0
C
K
7
6
5
4
3
2
1
0
CT
KO
RP
T
Table 15. WRITE WIPER CONTROL REGISTER (WCR)
S DEVICE ADDRESSES A
INSTRUCTION
A
DATA
AS
T
A
0 1 0 1 A3
A2
A1
A0
C
K
1
0
1
0
0
0
P1
P0
C
K
7
6
5
4
3
2
1
0
CT
KO
RP
T
Table 16. READ DATA REGISTER (DR)
S DEVICE ADDRESSES A
INSTRUCTION
A
DATA
AS
T
A
0
1
0
1
A3
A2
A1
A0
C
K
1
0
1
1
R1
R0
P1
P0
C
K
7
6
5
4
3
2
1
0
CT
KO
RP
T
Table 17. WRITE DATA REGISTER (DR)
S DEVICE ADDRESSES A
INSTRUCTION
A
DATA
AS
T
A
0
1
0
1
A3
A2
A1
A0
C
K
1
1
0
0
R1
R0
P1
P0
C
K
7
6
5
4
3
2
1
0
CT
KO
RP
T
Table 18. GANG TRANSFER DATA REGISTER (DR)
TO WIPER CONTROL REGISTER (WCR)
S DEVICE ADDRESSES A
INSTRUCTION
T
A
0 1 0 1 A3
A2
A1
A0
C
K
0
0
0
1
R1
R0
R
T
0
AS
0
CT
KO
P
http://onsemi.com
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| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet CAT5259.PDF ] | |
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