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PDF BD7185AGWL Data sheet ( Hoja de datos )
| Número de pieza | BD7185AGWL | |
| Descripción | Power Management LSI | |
| Fabricantes | ROHM Semiconductor | |
| Logotipo |  |
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Datasheet
Power Management LSI
for Mobile Phone
BD7185AGWL
General Description
The BD7185AGWL is an integrated Power Management
LSI available in a small 80-pins 0.4mm-pitch 3.8mm-by-
3.8mm Wafer-level CSP package, which is designed to
meet demands for space-constrained Smart phones.
The device provides 5-Buck Converters.
The device also includes 12 general-purpose LDOs
providing a wide range of voltage and current
capabilities.
All Buck Converters and LDOs are fully controllable by
the I2C interface. The BD7185AGWL is very easy to
use in any mobile platforms.
Features
5-channel high-efficiency Buck Converters
(16-step adjustable VO by I2C)
12-channel CMOS-type LDO
(16-step adjustable VO by I2C)
LDO and Buck Converter power ON/OFF control by
I2C interface or external pin.
Power ON/OFF sequence.
32.768kHz OSC and output buffer.
4-to-1 analog switch.
TCXO buffer.
SIM card I/F
I2C compatible Interface.
I2C device address changeable by ADRS pin.
(Device address is “1001011”,”1001100”)
Small and thin CSP package
(3.8mm X 3.8mm height 0.57mm max)
Applications
Smart Phones
Tablets
Mobile Router
Data Transmitter
Key Specifications
Input Voltage Range:
Output Voltage Range:
Switching Frequency:
OFF Current:
Operating Temperature Range:
2.6V to 5.5V
1.0V to 3.4V
2.0MHz(Typ)
0.3μA (Typ)
-35℃ to +85℃
Package
UCSP50L3C
W(Typ) x D(Typ) x H(Max)
3.80mm x 3.80mm x 0.57mm
○Product structure：Silicon monolithic integrated circuit
.www.rohm.com
© 2013 ROHM Co., Ltd. All rights reserved.
○This product is not designed protection against radioactive rays
1/75
TSZ02201-0Q4Q0AB00010-1-2
8.Apr.2014 Rev.001
1 page  
BD7185AGWL
Datasheet
Pin Description
Equivalent
Ball No. PIN Name A/D I/O Circuit
Eiqure
Function
A1
TEST1
--
-
Non connect pin
(Open or connected to GND.)
A2 LX4 A O A Inductor Connection for SWREG4
A3
PGND4
--
-
Ground for SWREG4
A4 LX3 A O A Inductor Connection for SWREG3
A5
PGND3
--
-
Ground for SWREG3
A6 LX2 A O A Inductor Connection for SWREG2
A7
PGND2
--
-
Ground for SWREG2
A8
PBAT1
--
-
Power Supply for SWREG1
A9
TEST2
--
-
Non connect pin
(Open or connected to GND)
B1 LX5 A O A Inductor Connection for SWREG5
B2 LX5 A O A Inductor Connection for SWREG5
B3
PBAT4
--
-
Power Supply for SWREG4
B4
PBAT3
--
-
Power Supply for SWREG3
B5 FB3 A I/O B Voltage Feed back pin for SWREG3
B6
PBAT2
--
-
Power Supply for SWREG2
B7 FB2 A I/O B Voltage Feed back pin for SWREG2
B8 FB1 A I/O B Voltage Feed back pin for SWREG1
B9
PGND1
--
-
Ground for SWREG1
C1
PGND5
--
-
Ground for SWREG5
C2
PGND5
--
-
Ground for SWREG5
C3 FB5 A I/O B Voltage Feed back pin for SWREG5
C4 FB4 A I/O B Voltage Feed back pin for SWREG4
C5
PSET
DI
C
LDO1 Initial voltage set pin
(L=1.8V, H=2.6V)
C6
ADRS
DI
C
Logic Selector
C7
SDA
DI
D
I2C data input
C8 SCL D I E
I2C clock input
C9 LX1 A O A Inductor Connection for SWREG1
Diode
+ side
- side
VBAT
GND
Initial
Condition
-
Function
(Note6)
PBAT4
PGND4
HiZ
PBAT4
GND
-
PBAT3
PGND3
HiZ
PBAT3
GND
-
PBAT2
PGND
HiZ
PBAT2
GND
-
-
VBAT
PGND1
GND
-
-
(Note6)
PBAT5
PGND5
HiZ
PBAT5
PGND5
HiZ
- PGND4 -
- PGND3 -
PBAT3
GND
-
- PGND2 -
PBAT2
GND
-
PBAT1
GND
-
PBAT1
GND
-
PBAT5
GND
-
PBAT5
GND
-
PBAT5
GND
-
PBAT4
GND
-
PBAT3
PBAT4
VBAT
GND
GND
GND
- Connect to GND
I2C Address
- 1001011 (ADRS=L)
1001100 (ADRS=H)
-
VBAT
GND
-
PBAT1
PGND1
HiZ
(Note 6) TEST1, TEST2, TEST3, TEST4, TEST5 and TEST6 are used for factory test mode. Please keep these pins open or connected to GND at all times.
○Product structure：Silicon monolithic integrated circuit
.www.rohm.com
© 2014 ROHM Co., Ltd. All rights reserved.
○This product is not designed protection against radioactive rays
5/75
TSZ02201-0Q4Q0AB00010-1-2
8.Apr.2014 Rev.001
5 Page 
BD7185AGWL
Datasheet
Initial Output Voltage Summary
Usage Example
Power
Supply
SWREG1
CORE
PBAT1
SWREG2
MEMORY
PBAT2
SWREG3
ANALOG
PBAT3
SWREG4
VIN2 power supply
(efficiency improvement)
PBAT4
SWREG5
VIN1 power supply
(efficiency improvement)
PBAT5
LDO1 I/O VIN1
LDO2
USB VBAT
LDO3
SIM I/F
VBAT
LDO4
Reserved
VIN1
LDO5
SYS PLL
VIN1
LDO6
Reserved
VIN1
LDO7
TCXO
VIN1
LDO8
2.5V R/F
VIN1
LDO9 LNA VIN1
LDO10
HKADC
VIN1
LDO11
RX PLL
VIN2
LDO12
TX PLL
VIN2
(Note 8) Initial output voltage depends on PSET pin setting.
SWREG Output Voltage Step Table
Initial Output Voltage
1.20V
1.80V
1.20V
1.40V
3.20V
2.60V / 1.80V (Note 8)
3.30V
1.80V
2.80V
1.20V
2.80V
2.80V
2.50V
2.80V
2.80V
1.20V
1.20V
Max Load
1.0A
0.5A
0.5A
0.5A
Adjustable Range
±50,100mV
±50,100mV
±50,100mV
±50,100mV
1.4A
300mA
50mA
50mA
300mA
150mA
150mA
50mA
150mA
150mA
150mA
150mA
150mA
±50,100mV
±50,100mV
±50,100mV
±50,100mV
±50,100mV
±50,100mV
±50,100mV
±50,100mV
±50,100mV
±50,100mV
±50,100mV
±50,100mV
±50,100mV
SWREG1 SWREG2 SWREG3 SWREG4 SWREG5
1.00
1.00
1.00
1.00
1.20
1.05
1.05
1.05
1.05
1.40
1.10
1.10
1.10
1.10
1.70
1.15
1.15
1.15
1.15
1.75
1.20
1.20
1.20
1.20
1.80
1.25
1.25
1.25
1.25
1.85
1.30
1.30
1.30
1.30
1.90
Voltage step 1.35 1.35 1.35 1.35 3.00
[V]
1.40
1.40
1.40
1.40
3.05
1.45
1.45
1.45
1.45
3.10
1.50
1.50
1.50
1.50
3.15
1.70
1.70
1.70
1.70
3.20
1.75
1.75
1.75
1.75
3.25
1.80
1.80
1.80
1.80
3.30
1.85
1.85
1.85
1.85
3.35
1.90
1.90
1.90
1.90
3.40
Voltage step
[V]
LDO1
1.70
1.75
1.80
1.85
1.90
2.50
2.55
2.60
2.65
2.70
2.80
2.90
2.95
3.00
3.05
3.10
LDO2
2.55
2.60
2.65
2.75
2.80
2.85
2.90
2.95
3.00
3.05
3.10
3.20
3.25
3.30
3.35
3.40
LDO3
1.70
1.75
1.80
1.85
1.90
2.50
2.60
2.70
2.80
2.90
2.95
3.00
3.05
3.10
3.20
3.30
LDO4
1.10
1.20
1.30
1.70
1.80
1.90
2.50
2.55
2.60
2.65
2.70
2.75
2.80
2.85
2.90
3.00
LDO5
1.00
1.05
1.10
1.15
1.20
1.25
1.30
1.70
1.80
1.90
2.60
2.70
2.80
2.90
3.00
3.10
LDO6
1.10
1.20
1.30
1.70
1.80
1.90
2.50
2.55
2.60
2.65
2.70
2.75
2.80
2.85
2.90
3.00
LDO7
1.10
1.20
1.30
1.70
1.80
1.90
2.50
2.55
2.60
2.65
2.70
2.75
2.80
2.85
2.90
3.00
LDO8
1.20
1.30
1.70
1.80
2.40
2.45
2.50
2.55
2.60
2.65
2.70
2.75
2.80
2.85
2.90
3.00
LDO9
1.10
1.20
1.30
1.70
1.80
1.90
2.50
2.55
2.60
2.65
2.70
2.75
2.80
2.85
2.90
3.00
LDO10
1.10
1.20
1.30
1.70
1.80
1.90
2.50
2.55
2.60
2.65
2.70
2.75
2.80
2.85
2.90
3.00
LDO11
1.00
1.05
1.10
1.15
1.20
1.25
1.30
1.35
LDO12
1.00
1.05
1.10
1.15
1.20
1.25
1.30
1.35
○Product structure：Silicon monolithic integrated circuit
.www.rohm.com
© 2014 ROHM Co., Ltd. All rights reserved.
○This product is not designed protection against radioactive rays
11/75
TSZ02201-0Q4Q0AB00010-1-2
8.Apr.2014 Rev.001
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet BD7185AGWL.PDF ] | |
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