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PDF SY100S834 Datasheet ( Hoja de datos )

Número de pieza SY100S834
Descripción Clock Generation Chip
Fabricantes Micrel Semiconductor 
Logotipo Micrel Semiconductor Logotipo

Total 8 Páginas
		
SY100S834 Hoja de datos, Descripción, Manual
SY100S834/SY100S834L
(÷1, ÷2, ÷4) or (÷2, ÷4, ÷8) Clock
Generation Chip
Precision Edge®
General Description
The SY100S834/L is low skew (÷1, ÷2, ÷4) or (÷2, ÷4, ÷8)
clock generation chip designed explicitly for low skew
clock generation applications. The internal dividers are
synchronous to each other, therefore, the common output
edges are all precisely aligned. The devices can be driven
by either a differential or single-ended ECL or, if positive
power supplies are used, PECL input signal. In addition,
by using the VBB output, a sinusoidal source can be AC-
coupled into the device. If a single-ended input is to be
used, the VBB output should be connected to the CLK
input and bypassed to ground via a 0.01µF capacitor. The
VBB output is designed to act as the switching reference
for the input of the SY100S834/L under single-ended input
conditions. As a result, this pin can only source/sink up to
0.5mA of current.
The Function Select (FSEL) input is used to determine
what clock generation chip function is. When FSEL input is
LOW, SY100S834/L functions as a divide by 2, by 4 and
by 8 clock generation chip. However, if FSEL input is
HIGH, it functions as a divide by 1, by 2 and by 4 clock
generation chip. This latter feature will increase the clock
frequency by two folds.
The common enable (EN) is synchronous so that the
internal dividers will only be enabled/disabled when the
internal clock is already in the LOW state. This avoids any
chance of generating a runt clock pulse on the internal
clock when the device is enabled/disabled as can happen
with an asynchronous control. An internal runt pulse could
lead to losing synchronization between the internal divider
stages. The internal enable flip-flop is clocked on the
falling edge of the input clock, therefore, all associated
specification limits are referenced to the negative edge of
the clock input.
Upon start-up, the internal flip-flops will attain a random
state; the master reset (MR) input allows for the
synchronization of the internal dividers, as well as for
multiple SY100S834/Ls in a system.
Data sheets and support documentation can be found on
Micrel’s web site at www.micrel.com.
Features
Precision Edge®
3.3V (SY100S834L) and 5V (SY100S834) power
supply options
50ps output-to-output skew
Synchronous enable/disable
Master reset for synchronization
Internal 75Kinput pulldown resistors
Available in 16-pin SOIC package
Truth Table
CLK
Z
ZZ
X
EN
L
H
X
Notes:
Z = LOW-to-HIGH transition.
ZZ = HIGH-to-LOW transition.
MR Function
L Divide
L Hold Q02
H Reset Q02
FSEL
Q0 Outputs Q1 Outputs Q2 Outputs
L Divide by 2 Divide by 4 Divide by 8
H Divide by 1 Divide by 2 Divide by 4
Precision Edge is a registered trademark of Micrel, Inc.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
June 2011
M9999-060911
hbwhelp@micrel.com or (408) 955-1690

1 page

SY100S834 pdf
Micrel, Inc.
SY100S834/SY100S834L
NECL Output DC Electrical Characteristics
VCC = GND; RL = 50to VCC 2V; VEE = 3.0V to 5.5V.
Symbol Parameter
TA = 40°C
Min. Typ. Max.
Min.
Power
IEE Supply
Current
− − 49
Output
VCH HIGH
1085 1005 880 1025
Voltage
Output
VOL LOW
1830 1695 1555 1830
Voltage
Input
VIH HIGH
1165
880 1165
Voltage
VIL
Input LOW
Voltage
1810 − −1475 1810
Output
VBB Reference 1.38 − −1.26 1.38
Voltage
Common
VCMR
Mode
Range(1)
1.3
0.4 1.4
Input
IIH HIGH
150
Current
IIL
Input LOW
Current
0.5
0.5
TA = 0°C
Typ.
955
1705
Max.
49
880
1620
880
1475
1.26
0.4
150
TA = +25°C
Min. Typ. Max.
− − 49
1025 955 880
1810 1705 1620
1165
880
1810 − −1475
1.38 − −1.26
1.4 − −0.4
− − 150
0.5
TA = +85°C
Min. Typ. Max.
− − 54
1025 955 880
1810 1705 1620
1165
880
1810 − −1475
1.38 − −1.26
1.4 − −0.4
− − 150
0.5
Unit
mA
V
V
V
V
V
V
µA
µA
Note:
1. The CMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the
specified range and the peak-to-peak voltage lies between VPP (min.) and 1V. The lower end of the CMR range varies 1:1 with VEE. The numbers in
the spec table assume a nominal VEE = 3.3V. Note for PECL operation, the VCMR (min.) will be fixed at 3.3V IVCMR (min.)I.
June 2011
5 M9999-060911
hbwhelp@micrel.com or (408) 955-1690

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