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PDF PL600-27T Datasheet ( Hoja de datos )

Número de pieza PL600-27T
Descripción Low Power 3 Output XO
Fabricantes Micrel Semiconductor 
Logotipo Micrel Semiconductor Logotipo

Total 7 Páginas
		
PL600-27T Hoja de datos, Descripción, Manual
FE AT UR E S
3 LVCMOS outputs with OE tri-state control
Low current consumption:
o <4.5mA @ 27MHz, 3.3V
10 to 52MHz fundamental crystal input
1 to 100MHz reference clock input
Accepts both LVCMOS and sine wave inputs
Low phase noise (-130 dBc @ 10kHz offset)
Low jitter (RMS): 2.5ps period jitter
12mA drive capability at TTL output
1.8V to 3.3V operation
Available in GREEN/RoHS 8-pin SOP and 6-pin
SOT23 packages
DESCRIPTION
The PL600-27T is a low cost XO IC, designed to re-
place multiple XO solutions saving the cost and
board space of clock distribution buffers. In addition,
it provides among the lowest current on the market
for the 10MHz to 52MHz range. The PL600-27T ac-
cepts crystal and clock inputs from 10 to 52MHz
(fundamental resonant mode crystal) and provides
low phase noise (<-130dBc at 10kHz offset at
30MHz), and very low jitter (2.5 ps RMS period jitter)
outputs.
PL600-27T
Low Power 3 Output XO
PIN ASSIGNMENT
XIN/FIN
OE^
CLK1
GND
1
2
3
4
8 XOUT
7 CLK0
6 VDD
5 CLK2
SOP-8L
^: Denotes internal Pull-up
CLK1 1 6 CLK2
GND 2 5 VDD
FIN 3 4 CLK0
SOT23-6L
BLOCK DIAGRAM
XIN/FIN
XOUT
Xtal
Osc
CLK0
CLK1
CLK2
OE
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 6/24/10 Page 1

1 page

PL600-27T pdf
PL600-27T
Low Power 3 Output XO
LAYOUT RECOMMENDATIONS
The following guidelines are to assist you with a pe rformance optimized PCB design:
Signal Integrity and Termination
Considerations
- Keep traces short!
- Trace = Inductor. With a capacitive load this equals
ringing!
- Long trace = Transmission Line. Without proper ter-
mination this will cause reflections ( looks like ringing ).
- Design long traces (> 1 inch) as “striplines” or
“microstrips” with defined impedance.
- Match trace at one side to avoid reflections bouncing
back and forth.
Decoupling and Power Supply
Considerations
- Place decoupling capacitors as close as possible to
the VDD pin(s) to limit noise from the power supply
- Multiple VDD pins should be decoupled separately
for best performance.
- Addition of a ferrite bead in series with VDD can
help prevent noise from other board sources
- Value of decoupling capacitor is frequency de-
pendant. Typical values to use are 0.1 F for de-
signs using frequencies < 50MHz and 0.01F for
designs using frequencies > 50MHz.
Typical LVCMOS termination
Place Series Resistor as close as possible to LVCMOS output
LVCMOS Output Buffer
( Typical buffer impedance 20 
50line
To LVCMOS Input
Series Resistor
Use value to match output
buffer impedance to 50
trace. Typical value 30
Crystal Tuning Circuit
Series and parallel capacitors used to fine tune the crystal load to the circuit load.
Crystal
Cst
XIN
1
Cpt
XOUT
8
Cpt
CST Series Capacitor, used to lower circuit load to match crystal load. Raises frequency
offset. This can be eliminated by using a crystal with a Cload of equal or greater value than the
oscillator.
CPT Parallel Capacitors, Used to raise the circuit load to match the crystal load. Lowers
frequency offset.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 6/24/10 Page 5

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