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Número de pieza 2EDN8524F
Descripción EiceDRIVER MOSFET
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EiceDRIVER™
2EDN752x / 2EDN852x
Fast, precise, strong and compatible
• Highly efficient SMPS enabled by 5 ns fast slew rates and 17 ns propagation delay precision for fast MOSFET
and GaN switching
• 1 ns channel-to-channel propagation delay accuracy enables safe use of two channels in parallel
• Two independent 5 A channels enable numerous deployment options
• Industry standard packages and pinout ease system-design upgrades
The new Reference in Ruggedness
• 4.2 V and 8 V UVLO (Under Voltage Lock Out) options ensure instant MOSFET protection under abnormal
conditions
• -10 V control and enable input robustness delivers crucial safety margin when driving pulse-transformers or
driving MOSFETs in through hole packaging
• 5 A reverse current robustness eliminates the need for output protection circuitry.
Typical Applications
• Server SMPS
• TeleCom SMPS
• DC-to-DC Converter
• Bricks
• Power Tools
• Industrial SMPS
• Motor Control
• Solar SMPS
Example Topologies
• Single and interleaved PFC
• LLC, ZVS with pulse transformer
• Synchronous Rectification
Description
The 2EDN752x/2EDN852x is an advanced dual-channel driver. It is suited to drive logic and normal level MOSFETs
and supports OptiMOSTM, CoolMOSTM, Standard Level MOSFETs, Superjunction MOSFETs, as well as IGBTs and
GaN Power devices.
The control and enable inputs are LV-TTL compatible (CMOS 3.3 V) with an input voltage range from -5 V to +20 V.
-10 V input pin robustness protects the driver against latch-up or electrical overstress which can be induced by
parasitic ground inductances. This greatly enhances system stability.
Data Sheet
Please read the Important Notice and Warnings at the end of this document
www.infineon.com
Revision 2.3
2016-10-05

1 page




2EDN8524F pdf
EiceDRIVER™
2EDN752x / 2EDN852x
Product Versions
1.1 Undervoltage Lockout Versions
The two Undervoltage Lockout versions are indicated by the variable x in the product version 2EDNy52x:
• y=7: lower voltage for logic level MOSFETs (4.2 V)
• y=8: higher voltage for standard and superjunction MOSFETs (8.0 V)
Please refer to the functional description section for more details in Chapter 4 (Undervoltage Lockout (UVLO)).
1.2 Logic Versions
The 2 logic versions are indicated by the variable x in the product version 2EDNy52x:
• x=3: inverting input logic
• x=4: non-inverting / direct input logic
The logic relations between inputs, enable pins and outputs are given in Table 2 for the inverting and non-
inverting version 2EDNx523 and 2EDNx524. The state of the driving output is defined by the state of the respective
input, if the enable inputs ENA and ENB are high (or left open). A logic “low” at an enable input or an undervoltage
lockout event, due to low voltage at VDD, causes the respective output to be low too, regardless of the input signal.
Functional description is shown in Chapter 3 ( Block Diagram) and Chapter 4 (Input Configurations).
Table 2 Logic Table
Inputs
Output Inverting
Output Standard
ENA ENB
INA
INB
UVLO1)
OUTA
OUTB
OUTA OUTB
xx
xx
active
L
L
LL
LL
xx
inactive L
L
LL
HL
Lx
inactive H
L
LL
HL
Hx
inactive L
L
HL
L H x L inactive L H
LL
L H x H inactive L L
LH
HH
LL
inactive H
H
LL
HH
HL
inactive L
H
HL
H H L H inactive H L
LH
HH
HH
inactive L
L
H
1) Inactive means that VDD is above UVLO threshold voltage and release logic to control output stage.
Active means that UVLO disable active the output stages.
H
1.3 Package Versions
The logic and UVLO versions are available in 3 different packages.
• a standard PG-DSO-8-60 (designated by “F”)
• a leadless PG-WSON-8-1 (designated by “G”)
• a small PG-TSSOP-8-1 (designated by “R”)
Drawings can be viewed in Chapter 8 (Outline Dimensions).
Data Sheet
5
Revision 2.3
2016-10-05

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2EDN8524F arduino
EiceDRIVER™
2EDN752x / 2EDN852x
Functional Description
4 Functional Description
4.1 Introduction
The 2EDN752x / 2EDN852x is a fast dual-channel driver for low-side switches. Two true rail-to-rail output stages
with very low output impedance and high current capability are chosen to ensure highest flexibility and cover a
high variety of applications.
The focus on robustness at the input and output side additionally gives this device a safety margin in critical
abnormal situations. An extended negative voltage range protects input pins against ground shifts. No current
flows over the ESD structure in the IC during a negative input level. All outputs are robust against reverse current.
The interaction with the power MOSFET, even reverse reflected power will be handled by the strong internal
output stage.
All inputs are compatible with LV-TTL signal levels. The threshold voltages with a typical hysteresis of 1.1 V are
kept constant over the supply voltage range.
Since the 2EDN752x / 2EDN852x aims particularly at fast-switching applications, signal delays and rise/fall times
have been minimized. Special effort has been made towards minimizing delay differences between the 2
channels to very low values of typically 1 ns.
4.2 Supply Voltage
The maximum supply voltage is 20 V. This high voltage can be valuable in order to exploit the full current
capability of 2EDN752x / 2EDN852x when driving very large MOSFETs. The minimum operating supply voltage is
set by the undervoltage lockout function to a typical default value of 4.2 V or of 8 V. This lockout function protects
power MOSFETs from running into linear mode with subsequent high power dissipation.
4.3 Input Configurations
As described in Chapter 1, 2EDN752x / 2EDN852x is available in 2 different configurations with respect to the logic
configuration of the 4 input pins (input plus enable).
The enable inputs are internally pulled up to a logic high voltage, i.e. the driver is enabled with these pins left
open. The direct PWM inputs are internally pulled down to a logic low voltage. This prevents a switch-on event
during power up and a not driven input condition. Version with inverted PWM input have an internal pull up
resistor to prevent unwanted switch-on.
All inputs are compatible with LV-TTL levels and provide a hysteresis of 1.1 V typ. This hysteresis is independent
of the supply voltage.
All input pins have a negative extended voltage range. This prevents cross current over single wires during GND
shifts between signal source (controller) and driver input.
4.4 Driver Outputs
The two rail-to-rail output stages realized with complementary MOS transistors are able to provide a typical 5 A
of sourcing and sinking current. This driver output stage has a shoot through protection and current limiting
behavior. After a switching event, current limitation is raised up to achieve the typical current peak for an
excellent fast reaction time of the following power MOS transistor.
The output impedance is very low with a typical value below 0.7 for the sourcing p-channel MOS and 0.5 for
the sinking n-channel MOS transistor. The use of a p-channel sourcing transistor is crucial for achieving true rail-
to-rail behaviour and avoiding a source follower’s voltage drop.
Data Sheet
11
Revision 2.3
2016-10-05

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