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PDF DM9106 Data sheet ( Hoja de datos )
| Número de pieza | DM9106 | |
| Descripción | 10/100 Mbps 3-port Ethernet Switch Controller | |
| Fabricantes | DAVICOM | |
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DAVICOM Semiconductor, Inc.
DM9106
10/100 Mbps 3-port Ethernet Switch Controller
with PCI Interface
DATA SHEET
Preliminary
Version: DM9106-DS-P01
July 9, 2009
1 page  
DM9106
3-port switch with PCI Interface
9. FUNCTIONAL DESCRIPTION....................................................................................... 64
9.1 PCI BUS BUFFER MANAGEMENT.................................................................................................................... 64
9.1.1. Overview ............................................................................................................................................. 64
9.1.2. Data Structure and Descriptor List...................................................................................................... 64
9.1.3. Buffer Management : Ring Structure Method ..................................................................................... 64
9.1.4. Buffer Management : Chain Structure Method ................................................................................... 64
9.1.5. Descriptor List: Buffer Descriptor Format ........................................................................................... 65
9.1.2. Transmit Data Buffer Processing........................................................................................................ 72
9.2 SWITCH FUNCTION:........................................................................................................................................ 73
9.2.1 Address Learning................................................................................................................................. 73
9.2.2 Address Aging...................................................................................................................................... 73
9.2.3 Packet Forwarding ............................................................................................................................... 73
9.2.4 Inter-Packet Gap (IPG) ........................................................................................................................ 73
9.2.5 Back-off Algorithm................................................................................................................................ 73
9.2.6 Late Collision ....................................................................................................................................... 73
9.2.7 Half Duplex Flow Control ..................................................................................................................... 73
9.2.8 Full Duplex Flow Control...................................................................................................................... 73
9.2.9 Partition Mode...................................................................................................................................... 73
9.2.10 Broadcast Storm Filtering .................................................................................................................. 74
9.2.11 Bandwidth Control ............................................................................................................................. 74
9.2.12 Port Monitoring Support..................................................................................................................... 74
9.2.13 VLAN Support .................................................................................................................................... 75
9.2.13.1 Port-Based VLAN ........................................................................................................................... 75
9.2.13.2 802.1Q-Based VLAN ...................................................................................................................... 75
9.2.13.3 Tag/Untag ....................................................................................................................................... 75
9.2.14 Priority Support .................................................................................................................................. 76
9.2.14.1 Port-Based Priority.......................................................................................................................... 76
9.2.14.2 802.1p-Based Priority ..................................................................................................................... 76
9.2.14.3 DiffServ-Based Priority ................................................................................................................... 76
9.3 MII INTERFACE .............................................................................................................................................. 77
9.3.1 MII data interface ................................................................................................................................. 77
9.3.2 MII Serial Management........................................................................................................................ 77
9.3.3 Serial Management Interface............................................................................................................... 78
Preliminary datasheet
DM9106-DS-P01
July 9, 2009
5
5 Page 
DM9106
3-port switch with PCI Interface
5. Pin Description
I = Input, O = Output, I/O = Input / Output, O/D = Open Drain, P = Power, PD=internal pull-low (about 50K Ohm)
# = asserted Low
5.1 PCI Bus interface
Pin No.
Pin Name
I/O
Description
2
IDSEL
I Initialization Device Select
This signal is asserted high during the Configuration Space
read/write access.
14
FRAME#
I/O Cycle Frame
This signal is driven low by the DM9106 master mode to
indicate the beginning and duration of a bus transaction.
15
IRDY#
I/O Initiator Ready
This signal is driven low when the master is ready to complete
the current data phase of the transaction. A data phase is
completed on any clock when both IRDY# and TRDY# are
sampled asserted.
16
TRDY#
I/O Target Ready
17
19
20
22
23
1,13,25,36
DEVSEL#
STOP#
PERR#
SERR#
PAR
C/BE3#
C/BE2#
C/BE1#
C/BE0#
This signal is driven low when the target is ready to complete
the current data phase of the transaction. During a read, it
indicates that valid data is asserted. During a write, it indicates
that the target is prepared to accept data.
I/O Device Select
The DM9106 asserts the signal low when it recognizes its
target address after FRAME# is asserted. As a bus master, the
DM9106 will sample this signal which insures its destination
address of the data transfer is recognized by a target.
I/O Stop
This signal is asserted low by the target device to request the
master device to stop the current transaction.
I/O Parity Error
The DM9106 as a master or slave will assert this signal low to
indicate a parity error on any incoming data.
I/O System Error
This signal is asserted low when address parity is detected with
enabled PCICS bit31 (detected parity error.) The system error
asserts two clock cycles after the falling address if an address
parity error is detected.
I/O Parity
This signal indicates even parity across AD0~AD31 and
C/BE0#~C/BE3# including the PAR pin. This signal is an
output for the master and an input for the slave device. It is
stable and valid one clock after the address phase.
I/O Bus Command/Byte Enable
During the address phase, these signals define the bus
command or the type of bus transaction that will take place.
During the data phase these pins indicate which byte lanes
contain valid data. C/BE0# applies to bit7-0 and C/BE3#
applies to bit31-24.
Preliminary datasheet
DM9106-DS-P01
July 9, 2009
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet DM9106.PDF ] | |
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