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PDF DM9162I Data sheet ( Hoja de datos )

Número de pieza DM9162I
Descripción Industrial-Temperature 10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
Fabricantes DAVICOM 
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No Preview Available ! DM9162I Hoja de datos, Descripción, Manual

DM9162/DM9162I
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
DAVICOM Semiconductor, Inc.
DM9162/DM9162I
Industrial-Temperature 10/100 Mbps Fast Ethernet
Physical Layer Single Chip Transceiver
DATA SHEET
Preliminary
Version: DM9162-DS-P03
September 19, 2016
1 Preliminary
Version: DM9162-DS-12-P03
September 19, 2016

1 page




DM9162I pdf
3. Block Diagram
DM9162/DM9162I
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
MII
Signals
25M OSCI
TX CGM
LED1-4#
LED
Driver
4B/5B
Encoder
Scram bler
Parallel
to Serial
NRZ
to
NRZI
NRZI to
MLT-3
MLT-3
Driver
100TXD+/-
MII
Interface/
Control
25M CLK
Rise/Fall
Tim e
CTL
125M CLK
AutoMDIX
4B/5B
Decoder
Code-
group
Alignm ent
Des cram bler
Serial to
Parallel
Digital
Logic
NRZI
to
NRZ
RX
CRM
MLT-3 to
NRZI
Adaptive
EQ
RXI+/-
10BASE-T
Module
RX
TX
RXI+/-
10TXD+/-
Regis ter
Collision
Detection
Carrier
Sens e
Auto-
Negotiation
5 Preliminary
Version: DM9162-DS-12-P03
September 19, 2016

5 Page





DM9162I arduino
DM9162/DM9162I
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
14 -
39 -
45 -
5.5 Bias and Clock
Pin No.
Pin No.
48-pin
32-pin
47 -
48 1
43,42
32,31
CABLESTS
/LINKSTS
DISMDIX
SD
O, Cable Status or Link Status
LI This pin is used to indicate the status of the cable connection
(D) when power up reset latch low (Default), (QFN-32 is Pull-
down)
0 = Without cable connection
1 = With cable connection
This pin is used to indicate the status of the Link connection
when power up reset latch high,
0 = With link
1 = Without link
I HP Auto-MDIX Control (QFN-32 is Pull-down)
(D) 1: Disable auto mode
0: Enable HP Auto-MDIX mode
I Signal detect for fiber (QFN-32: Auto detect)
Pin Name I/O
Description
BGRESG
BGRES
XT1,XT2
P Band gap Ground
O Band gap Voltage Reference Resistor 6.8K ohm +/- 1%
I Reference Clock Input
When in Normal MII mode or
when in Reduced MII mode and pin TXCLK is latched high at
the end of reset:
A 25MHz crystal or oscillator as DM9162 reference clock is
used. If the crystal is used, it is connected across pins XT1
and XT2. If the oscillator is used, it can either connect to pin
XT1 (left pin XT2 unconnected) or to pin XT2 (left pin XT1
unconnected).
5.6 Power
Pin No.
48-pin
1,2,9
5
6
46
23,30
41
15,33,44
Pin No.
32-pin
6
*1
*1
*1
23
30
*1
When in Reduced MII mode and pin TXCLK is latched low at
the end of reset:
A 50MHz oscillator is used, and it can either connect to pin
XT1 (left pin XT2 unconnected) or to pin XT2 (left pin XT1
unconnected).
*Note: Please see 10. RMII application for detail connection.
Pin Name I/O
Description
AVDD18
AGND
AGND
AGND
DVDD33
VDD33
DGND
P Analog 1.8V Regulator Power output
P Analog Receive Ground
P Analog Transmit Ground
P Analog Substrate Ground
P Digital Power
P Digital Power for Crystal
P Digital Ground or QFN package Ground
*1: The DM9162 IC employs a QFN package, which means the absence of a pin dedicated to ground (GND). In
the QFN package, the GND is located at the bottom of the IC directly in the middle. The large light-colored
square is where the GND is connected.
11 Preliminary
Version: DM9162-DS-12-P03
September 19, 2016

11 Page







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